Simultaneous Reduction of Dynamic and Static Power in Scan Structures

Sharifi, Shervin; Jaffari, Javid; Hosseinabady, Mohammad; Afzali-Kusha, Ali; Navabi, Zainalabedin

doi:10.1109/date.2005.270

Cited by 28 publications

(19 citation statements)

References 15 publications

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“…In addition, the transmission gate is a strong driver that feeds the gating logic inverter and pseudo primary inputs during normal/capture mode. Partial gating methods [35][36][37][38][39] have been proposed to reduce the full gating penalties in area overhead and performance degradation. By having the proper selection of scan cells on non-critical paths to be gated and their gating values, they try to maximize the shift power reduction with acceptable performance degradation.…”

Section: Proposed Low Power Gating Scan Cellmentioning

confidence: 99%

The Design and Implementation of a Low-Power Gating Scan Element in 32/28 nm CMOS Technology

Naeini

Dass²,

Ooi

2017

JLPEA

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Abstract:Excessive power consumption during test application time has severely negative effects on chip reliability since it has an inevitable role in hot spots that appear, degradation of performance, circuit premature destruction, and functional failures. In scan-based designs, rippling transitions caused by test patterns shifting along the scan chain not only elevate power consumption in the scan chain but also introduce spurious switching activities in the combinational logic. In this work, a new low power gating scan cell for scan based designs has been proposed in order to reduce power consumption in the scan chain as well as the combinational part during shifting. We have modified the conventional scan cell and augmented it with state preserving and gating logic that enables an average power reduction in combinational logic during shift mode. The new scan cell mitigates the number of transitions during shift and capture cycles. Thus, it reduces the average power consumption inside the scan cell and as a result the scan chain during scan shifting with a low impact on peak power during the capture cycle. Furthermore, due to introducing a new shorter shift path, improvements are observed in terms of propagation delay and power consumption in the scan chain during shifting. This leads to higher feasible shift frequency whereby the shift frequency is limited by the maximum power budget and hence results in reducing the test application time. The post-layout spice simulation results show a 7.21% reduction in total power consumption, an average 12.25% reduction of shift power consumption, and a 50.7% improvement in the clock (CLK)-to-shift propagation delay over the conventional scan cell in Synopsys 32/28 nm standard CMOS technology.

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Section: Proposed Low Power Gating Scan Cellmentioning

confidence: 99%

The Design and Implementation of a Low-Power Gating Scan Element in 32/28 nm CMOS Technology

Naeini

Dass²,

Ooi

2017

JLPEA

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“…Scan based structural testing is the most popular approach in industry [8] [9]. In [9], a scheme has been presented for simultaneous reduction in dynamic and static power in scan chains.…”

Section: Introductionmentioning

confidence: 99%

“…In [9], a scheme has been presented for simultaneous reduction in dynamic and static power in scan chains. The authors have used low leakage blocking pattern in conjunction with non-critical inputs only.…”

Section: Introductionmentioning

confidence: 99%

Test Pattern Selection and Customization Targeting Reduced Dynamic and Leakage Power Consumption

Kundu

Kumar²,

Chattopadhyay

2009

2009 Asian Test Symposium

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Test mode power dissipation has been found to be much more than the functional power dissipation. Since dynamic power dissipation had a major contribution to the heat generated, most of the studies focused on reducing the transitions during testing. But at submicron technology, leakage current becomes significantly high. This demands a control on the leakage current as well. In this work, we propose techniques to simultaneously reduce the switching activity and keeping the leakage current under check. The overall average switching activity reduction is 70.01% and reduction in leakage power is about 6.31%, the maximum being 99.33% in switching and 9.92% in leakage.

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“…In [5] and [9] methods to select primary input values to reduce switching activity during scan shift as well as reduce leakage current have been proposed. Work in [10] proposes ordering tests to reduce switching activity during scan shift. Work in [11] proposes reducing the scan shift frequency to reduce dynamic power consumption during scan shift.…”

Section: Introductionmentioning

confidence: 99%

“…Several methods to reduce switching activity during scan based test have been proposed [5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20]. Methods proposed in [5][6][7][8] make modifications to scan chains to facilitate reduction of switching activity during scan shift.…”

Section: Introductionmentioning

confidence: 99%

Enhancing delay fault coverage through low-power segmented scan

Zhang

Reddy

Pomeranz³

et al. 2007

IET Comput. Digit. Tech.

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-Reducing power dissipation during test has been an active area of academic and industrial research for the last few years and numerous low power DFT techniques and test generation procedures have been proposed. Segmented scan [17][18][19][20] has been shown to be an effective technique in addressing test power issues in industrial designs [18]. To achieve higher shipped product quality, tests for delay faults are becoming essential components of manufacturing test. This paper demonstrates, for the first time, that segmented scan facilitates increased delay fault without degrading the reduction of the switching activity obtained by segmented scan. The increased transition delay fault coverage is achieved through careful selection of the capture cycle application. Experimental results on larger ISCAS-89 benchmarks show that using three segments, on average, fault coverage using launch off capture can be increased by about 5.8% while simultaneously reducing the peak switching activity caused by capture cycles by over 24.8%.

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Simultaneous Reduction of Dynamic and Static Power in Scan Structures

Abstract: Abstract

Cited by 28 publications

References 15 publications

The Design and Implementation of a Low-Power Gating Scan Element in 32/28 nm CMOS Technology

The Design and Implementation of a Low-Power Gating Scan Element in 32/28 nm CMOS Technology

Test Pattern Selection and Customization Targeting Reduced Dynamic and Leakage Power Consumption

Enhancing delay fault coverage through low-power segmented scan

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