Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors

IEEE Trans. Nanotechnology

Micheli

2015

Self Cite

Abstract-Controllable-polarity silicon nanowire transistors (CPSiNWFETs) are among the promising candidates to complement or even replace the current CMOS technology in the near future. Polarity control is a desirable property that allows the online configuration of the device polarity. CP-SiNWFETs result in smaller and faster logic gates unachievable with conventional CMOS implementations. From a circuit testing point of view, it is unclear if the current CMOS and FinFET fault models are comprehensive enough to model all the defects of CP-SiNWFETs. In this paper, we explore the possible manufacturing defects of this technology through analyzing the fabrication steps and the layout structure of logic gates. Using the obtained defects, we then evaluate their impacts on the performance and the functionality of CP-SiNWFET logic gates. Out of the results, we extend the current fault model to a new a hybrid model, including stuck at p-type and stuck-at ntype, which can be efficiently used to test the logic circuits in this technology. The newly introduced fault model can be utilized to adequately capture the malfunction behavior of CP logic gates in the presence of nanowire break, bridge, and float defects. Moreover, the simulations revealed that the current CMOS test methods are insufficient to cover all faults, i.e., stuck-Open. We proposed an appropriate test method to capture such faults as well.Index Terms-Controllable-polarity silicon nanowires, defect, fault model, gate oxide short, nanotechnology.

“…3. Layouts of the NOR (a) and 2-input XOR (b) based on the SoT method [35], [36] with several possible defects. logic cell) and become very challenging for emerging technologies.…”

Section: B Logic Cell Defectsmentioning

confidence: 99%

“…3 represents the layouts of two TIG-based logic cells ((a) NOR gate and (b) 2-input XOR) with some highlighted possible defects. Note that the presented layouts rely on the sea-of-tile (SoT) physical design methodology presented in [35] and [36].…”

Section: B Logic Cell Defectsmentioning

confidence: 99%

From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires

Mohammadi

IEEE Trans. Nanotechnology

Micheli

2015

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“…3b. Such a scheme was first sketched in [5]. This power routing distributes one of the power signals (here V DD ) with vertical rails of metal2, in order to decongest the local routing interconnections of fixed polarity biases.…”

Section: A Grid-based Power Routing Schemementioning

confidence: 99%

“…This approach was first presented in [5]. Here, we propose a complete study of its impact on the metal distribution and performance of designs using SiNWFETs compared to standard approaches.…”

Section: Introduction the Performance And Power Consumption Limitsmentioning

confidence: 99%

Novel grid-based power routing scheme for regular controllable-polarity FET arrangements

Zografos

2014 IEEE International Symposium on Circuits and Systems (ISCAS)

Micheli

2014

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Abstract-Polarity-controllable transistors have emerged in the last few years as an adequate successor of current CMOS FinFETs. Due to the additional polarity terminal, novel physical design techniques are required. We present a novel grid-based power routing scheme able to mitigate the polarity terminal impact. The logic cells are organized in regular arrangements and easily configured using the novel power routing scheme. The impact of the placement and routing techniques used is gauged in terms of routing metal distribution, speed and area performance. Benchmark circuits are synthesized, placed and routed using commercial tools and performances are extracted. Post place and route results show 28% faster circuits compared to 22nm FinFET regular layout-based designs.

“…These transistors enable a dynamic majority carrier selection and so, provide on-demand n-type/p-type MOS transistor behavior. While PCT have been actively studied for digital circuit design in order to reduce the computation logic area and complexity [11] [12] [13] [14], PCT-based memories, and particularly Non-Volatile Memories (NVM) have been poorly studied. To the extent of our knowledge, only [15] proposed a NVM architecture using PCT and Spin Transfer Torque (STT-MRAM) memory technology to increase the security of memories.…”

Section: Introductionmentioning

confidence: 99%

Resistive Switching Memory Architecture Based on Polarity Controllable Selectors

Levisse

IEEE Trans. Nanotechnology

Giraud

et al. 2019

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With the continuous scaling of CMOS technology, integrating an embedded high-density non-volatile memory appears to be more and more costly and technologically challenging. Beyond floating-gate memory technologies, bipolar Resistive Random Access Memories (RRAM) appear to be one of the most promising technologies. However, when organized in a 1 or 2-Transistor 1-RRAM (1T1R, 2T1R) architectures, they suffer from large bitcell area, degraded performance and reliability issue during reset operation. The association of multiple-independentgate Polarity Controllable Transistors (PCT) with RRAM overcomes these drawbacks, while providing a dense structure. In this paper, we present two innovative PCT-based bitcells and propose an extensive study of their functionality, physical design considerations and performances in read and write operations compared to CMOS-based 1T1R and 2T1R bitcells. The proposed bitcells outperform the performances of 1T1R and 2T1R bitcells in reset (5× to 105× speed improvement) are competitive in term of area (1.35× to 2.6× area reduction versus 2T1R) and avoid gate overdrive (1.2V versus more than 2V in 1T1R bitcells) thus reducing selector reliability concerns. We also propose an innovative programming strategy which takes advantage of the PCT polarity control and enabling 500× improvement in reset performance. Finally, the proposed bitcells performs 15 to 67% faster than CMOS bitcells in read.