Process Development and Optimization for 3 <inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> High Aspect Ratio Via-Middle Through-Silicon Vias at Wafer Level
“…The conformal coverage of 100-nm ALD dielectric oxide layer is deposited around TSV with the dimensions of 3 × 50 μm, and the thickness of the oxide layer on sidewall and bottom are approximately 95 nm, as shown in Fig. 2 [11]. The aspect ratio (AR) of TSV is 17, and the result demonstrates an excellent profile as a dielectric layer for miniature TSV applications.Fig.…”
Section: Tsv Dielectric Layermentioning
confidence: 99%
“…2Cross-sectional SEM images for a 3 × 50 μm TSV after ALD dielectric oxide layer deposition. a – d 91∼95-nm-thick film around TSV [11]
…”
3D integration with through-silicon via (TSV) is a promising candidate to perform system-level integration with smaller package size, higher interconnection density, and better performance. TSV fabrication is the key technology to permit communications between various strata of the 3D integration system. TSV fabrication steps, such as etching, isolation, metallization processes, and related failure modes, as well as other characterizations are discussed in this invited review paper.
“…The conformal coverage of 100-nm ALD dielectric oxide layer is deposited around TSV with the dimensions of 3 × 50 μm, and the thickness of the oxide layer on sidewall and bottom are approximately 95 nm, as shown in Fig. 2 [11]. The aspect ratio (AR) of TSV is 17, and the result demonstrates an excellent profile as a dielectric layer for miniature TSV applications.Fig.…”
Section: Tsv Dielectric Layermentioning
confidence: 99%
“…2Cross-sectional SEM images for a 3 × 50 μm TSV after ALD dielectric oxide layer deposition. a – d 91∼95-nm-thick film around TSV [11]
…”
3D integration with through-silicon via (TSV) is a promising candidate to perform system-level integration with smaller package size, higher interconnection density, and better performance. TSV fabrication is the key technology to permit communications between various strata of the 3D integration system. TSV fabrication steps, such as etching, isolation, metallization processes, and related failure modes, as well as other characterizations are discussed in this invited review paper.
“…On the other hand, DRIE process optimization for hole arrays was primarily done at the 10 micronscale to fabricate through-silicon-via, and aspect ratios of up to 26 have been achieved for 15-μm diameter hole arrays [8,14,15]. In order to increase the density of vias, DRIE process optimization was carried out on 1 micronscale and aspect ratios of up to 17 have been achieved for 2 and 3-μm diameter hole arrays [16,17]. However, the cross-sectional area of the hole array diminishes as the aspect ratio increases, resulting in a bottom that is less than half of the top.…”
During deep reactive ion etching (DRIE), microscale etch masks with small opening such as trenches or holes suffer from limited aspect ratio because diffusion of reactive ions and free radicals become progressively difficult as the number of DRIE cycle increases. For this reason, high aspect ratio structures of microscale trenches or holes are not readily available with standard DRIE recipes and microscale holes are more problematic than trenches due to omnidirectional confinement. In this letter, we propose an optimization for fabrication of high aspect ratio microscale hole arrays with an improved cross-sectional etch profile. Bias voltage and inductively coupled plasma power are considered as optimization parameters to promote the bottom etching of the high aspect ratio hole array. In addition, flow rates of octafluorocyclobutane (C$$_{4}$$
4
F$$_{8}$$
8
) and sulfur hexafluoride (SF$$_{6}$$
6
) for passivation and depassivation steps, respectively, are considered as optimization parameters to reduce the etch undercut. As a result of optimization, the aspect ratio of 20 is achieved for 1.3 μm-diameter hole array and etch area reduction at the bottom relative to the top is improved to 21%.
“…The widely used method is to use a scanning electron microscope (SEM), which features extremely high spatial resolution down to the nanometre scale, and specializes in surface morphology like sidewall scalloping roughness (Ham et al, 2011;Inoue et al, 2013) and deposition failure of the barrier layer (Zhang et al, 2015). However, SEM imaging analysis of the cross section of the TSV is destructive, time consuming and depends on the sample-cutting technique (Fursenko et al, 2015).…”
Comprehensive evaluation of through-silicon via (TSV) reliability often requires deterministic and 3D descriptions of local morphological and statistical features of via formation with the Bosch process. Here, a highly sensitive phase-contrast X-ray microtomography approach is presented based on recorrection of abnormal projections, which provides comprehensive and quantitative characterization of TSV etching performance. The key idea is to replace the abnormal projections at specific angles in principles of linear interpolation of neighboring projections, and to distinguish the interface between silicon and air by using phase-retrieval algorithms. It is demonstrated that such a scheme achieves high accuracy in obtaining the etch profile based on the 3D microstructure of the vias, including diameter, bottom curvature radius, depth and sidewall angle. More importantly, the 3D profile error of the via sidewall and the consistency of parameters among all the vias are achieved and analyzed statistically. The datasets in the results and the 3D microstructure can be applied directly to a reference and model for further finite element analysis. This method is general and has potentially broad applications in 3D integrated circuits.
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