Process evaluation in FinFET based 7T SRAM cell

Kumar, T. Santosh; Tripathi, Suman Lata

doi:10.1007/s10470-021-01938-4

Cited by 18 publications

(2 citation statements)

References 22 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…To address the issues with power usage, a FinFET based carry select adder (CSA) is proposed which consumes less power than MOSFET [4]. On a structural level, the Fin-FET is one of the most famous innovations of the fin-type FET, features a thin silicon body covered in gate electrodes or by biasing it individually, the leakage current may be reduced [5]. The most fundamental arithmetic operation is addition, and several adders are utilized in VLSI.…”

Section: Introductionmentioning

confidence: 99%

A new Excess-1 circuit based High-Speed Carry Select Adder in 18 nm FinFET Technology

Battini

PASHYA

Sivani

2023

Preprint

View full text Add to dashboard Cite

Conventional carry select adder (CCSA) uses a multiplexer in the final stage to select either an excess-1 result or a normal result. To improve the delay and number of transistors a new topology is Proposed (PCSA) that uses only a single type of cell i.e., a 2 − 1 multiplexer. The 2 − 1 multiplexer is constructed in CMOS and TGL logic styles using 18nm FinFETs. The sub-blocks such as half adder and excess-1 circuit used in this PCSA is realized using only a 2:1 multiplexer. Due to the usage of a single type 2:1 multiplexer, the PCSA exhibits better circuit regularity. The new topology of PCSA is designed using FinFET-based TGL and CMOS styles. All the adders such 4- and 8-bit are designed, simulated, and analyzed using Cadence Virtuoso, ADEL, and ADEXL at 18nm FinFET technology. The result analysis reveals that the speed performance and the number of transistors of 8-bit PCSA are better by 44.02% and 4% respectively compared to existing adders.

show abstract

Section: Introductionmentioning

confidence: 99%

A new Excess-1 circuit based High-Speed Carry Select Adder in 18 nm FinFET Technology

Battini

PASHYA

Sivani

2023

Preprint

View full text Add to dashboard Cite

show abstract

“…Static random access memory (SRAM) is used as CPU cache memory, occupying over half of the System-on-Chip (SoC) die area. The high density of SRAM with nanosized transistors is vulnerable to variability due to process variations and short-channel effects such as drain-induced barrier lowering (DIBL), non-ideal subthreshold swing ( SS ), and threshold voltage (V th ) roll-off [ 1 , 2 , 3 , 4 ]. The fin field-effect transistor (FinFET)-based SRAM has been adopted to overcome the problems of planar SRAM [ 5 ].…”

Section: Introductionmentioning

confidence: 99%

Performance Degradation in Static Random Access Memory of 10 nm Node FinFET Owing to Displacement Defects

Bang

Lee

et al. 2023

Micromachines

View full text Add to dashboard Cite

We comprehensively investigate displacement-defect-induced current and static noise margin variations in six-transistor (6T) static random access memory (SRAM) based on a 10 nm node fin field-effect transistor (FinFET) using technology computer-aided design (TCAD). Various defect cluster conditions and fin structures are considered as variables to estimate the worst-case scenario for displacement defects. The rectangular defect clusters capture more widely distributed charges at the fin top, reducing the on- and off-current. The read static noise margin (RSNM) is the most degraded in the pull-down transistor during the read operation. The increased fin width decreases the RSNM due to the gate field. The current per cross-sectional area increases when the fin height decreases, but the energy barrier lowering by the gate field is similar. Therefore, the reduced fin width and increased fin height structure suit the 10 nm node FinFET 6T SRAMs with high radiation hardness.

show abstract