Process Integration and Manufacturasility Issues for High Performance Multilevel Interconnect

Abstract

Interconnect delay is shown to be a performance-limiting factor for ULSI circuits when feature size is scaled into the deep submicron region, due to a rapid increase in interconnect resistivity and capacitance. Dielectric materials with lower values of permittivity are needed to reduce the line-to-line capacitance as metal spacing decreases. However, the challenge is to successfully integrate these materials into on-chip interconnects. A new multilevel interconnect scheme has been developed that gives improved performance through insertion of a low-dielectric-constant material between metal leads. A novel polymer/Si02 composite dielectric structure provides lower line-to-line capacitance while alleviating many of the integration and reliability problems associated with polymers in standard interconnect processing.

Electrical characterization of a‐C:H as a dielectric material in metal/insulator/metal structures

“…This work corroborates some of the L.H. Chou´s results [12], where it was shown that the conductivity of carbon PECVD films depends on the sp 2 and sp 3 bonds concentration, which are a consequence of the hydrogen content.…”

“…1 Introduction Since a decade ago, several insulating materials presenting a low dielectric permittivity (K) have been proposed for the back end of line (BOL) technology in order to reduce the crosstalk capacitance and RC delays associated with the inter-metallic levels [1,2]. However, the microelectronics industry has kept its interest in the well established SiO 2 related dielectrics.…”

Copper metallization for ULSL and beyond

“…This is shown in Figure 1, where both the interconnection delay and the intrinsic gate (MOS) delay are plotted as a function of the feature size (channel length). 8 It is clear that below about 0.5-pm feature size, the interconnection delay will be the performance limiter for the circuits.…”

Carbon films deposited by low frequency plasma as inter-metal dielectric

“…Interconnect capacitance increases as a result of the reduction in the metal pitch by scaling down the fabrication technology. Recently, new insulating materials for back end technology such as low-K dielectrics have been proposed, which reduce the interconnect capacitance, hence RC delay [1,2] and cross-talk noise to enhance circuit performance. However, many challenges remain in identifying a good low-K material that has the reliability required for manufacturing.…”