No abstract

Electromigration results have provided clear evidence of a short or “Blech” length effect in dual- damascene, Cu/oxide, multilinked interconnects. The test structure incorporates a repeated chain of Blech-type line elements and is amenable to failure analysis tools such as focused ion beam imaging. This large interconnect ensemble provides a statistical representation of electromigrationinduced damage in the regime where steady-state interconnect stress is manifest. Statistical analysis yields a critical length of 90 μm for interconnects with line width 0.5 μm at j=1.0×106 A/cm2 and T=325 °C.

An electromigration study has determined the lifetime characteristics and failure mode of dual-damascene Cu/oxide interconnects at temperatures ranging between 200 and 325 °C at a current density of 1.0 MA/cm2. A novel test structure design is used which incorporates a repeated chain of “Blech-type” line elements. The large interconnect ensemble permits a statistical approach to addressing interconnect reliability issues using typical failure analysis tools such as focused ion beam imaging. The larger sample size of the test structure thus enables efficient identification of “early failure” or extrinsic modes of interconnect failure associated with process development. The analysis so far indicates that two major damage modes are observable: (1) via-voiding and (2) voiding within the damascene trench.

Interconnect delay is shown to be a performance-limiting factor for ULSI circuits when feature size is scaled into the deep submicron region, due to a rapid increase in interconnect resistivity and capacitance. Dielectric materials with lower values of permittivity are needed to reduce the line-to-line capacitance as metal spacing decreases. However, the challenge is to successfully integrate these materials into on-chip interconnects. A new multilevel interconnect scheme has been developed that gives improved performance through insertion of a low-dielectric-constant material between metal leads. A novel polymer/Si02 composite dielectric structure provides lower line-to-line capacitance while alleviating many of the integration and reliability problems associated with polymers in standard interconnect processing.