Process liability evaluation for beyond 22nm node using EUVL

Tawarayama, Kazuo; Aoyama, Hajime; Matsunaga, Kentaro; Arisawa, Yukiyasu; Uno, Taiga; Magoshi, Shunko; Kyoh, Suigen; Nakajima, Yumi; Inanami, Ryoichi; Tanaka, Satoshi; Kobiki, Ayumi; Kikuchi, Yukiko; Kawamura, Daisuke; Takai, Kosuke; Murano, Koji; Hayashi, Yuichiro; Mori, Ikue

doi:10.1117/12.846265

Cited by 6 publications

(6 citation statements)

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“…22) However, for the etching process, a sufficient resist thickness is needed for its process step. In the case of a previous trial, 21) as shown Fig. 8(a), a 30 nm L&S pattern is well fabricated after the RIE process, but below 28 nm, the fabricated pattern is deformed because of insufficient resist thickness after development of the resist pattern.…”

Section: Etching Process Optimizationmentioning

confidence: 92%

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Application of Extreme Ultraviolet Lithography to Test Chip Fabrication

Tawarayama¹,

Nakajima

Kyoh

et al. 2011

Jpn. J. Appl. Phys.

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Extreme ultraviolet (EUV) lithography is considered to be the most promising technology for meeting the lithographic challenges posed by the next generation semiconductor design rule beyond a half pitch (hp) of 22 nm. A key area of the Selete EUV program is proof of manufacturability, which means verification of module integration for EUV lithography. To accomplish this, many technologies [e.g., mask, exposure tool, resist, optical proximity correction (OPC)] need to be developed and integrated. In this paper, we discuss the current status of each of them. To verify EUV's manufacturability, we applied EUV to test chip fabrication, metal wiring fabrication, and electrical measurement. The yield number of the hp 28 nm pattern is 70% after improving the resist and the etching process. These results show demonstrate that EUV lithography is a practical technology that is now suitable for semiconductor devices for 2x nm area.

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Section: Etching Process Optimizationmentioning

confidence: 92%

“…Our previous trial produced our first results for the 32 nm node. 21) We evaluated the same TEG in two more trials, while continually improving the resist process. Those trials provided increasing yields.…”

Section: Introductionmentioning

confidence: 99%

Application of Extreme Ultraviolet Lithography to Test Chip Fabrication

Tawarayama¹,

Nakajima

Kyoh

et al. 2011

Jpn. J. Appl. Phys.

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“…Table 1 shows the process conditions used in this evaluation. Selete standard resist 4 (SSR4), Selete standard resist 5 (SSR5) and Selete standard resist 6 (SSR6) were coated on 300mm Si substrate and exposed by full-field exposure tool (EUV1: Nikon) in Selete [6][7][8] . And the samples were developed with SOKUDO Track.…”

Section: Introductionmentioning

confidence: 99%

Study of post-develop defect on typical EUV resist

Harumoto¹,

Suyama²,

Miyagi³

et al. 2011

SPIE Proceedings

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This study reports on post-develop defect for EUV resist process. Presently, research and development of EUV resists are continuously being carried out in terms of resolution, sensitivity, LWR [1,2] . However, in the preparation of EUV lithography for mass-production, research on the reduction of pattern defects, especially post-develop defect is also necessary. As observed during the early stages of resist development for the various lithographic technologies, a large number of pattern defects are commonly coming from the resist dissolution process.As previously reported, utilizing an EUV exposure tool, we have classified several EUV specific defects on exposed and un-exposed area. And also we have reported approaches of defect reduction. [3] In this work, using some types developer solution (TBAH, TBAH+, etc) comparing with current developer solution (TMAH), EUV specific defects were evaluated. Furthermore, we investigated the defect appearing-mechanism and approached defect reduction by track process. Finally, based on these results, the direction of defect reduction approaches applicable for EUV resist processing was discussed.

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“…The most important unit of exposure tools is PO, in which the wavefront error of 0.4nmRMS and the flare of 6% were achieved 2 . EUV1 was used by Selete and the other customers for the development of EUV lithography process integration of 3X-nm-node and 2X-nm-node semiconductor devices [3][4][5][6][7][8][9][10] .…”

Section: Introductionmentioning

confidence: 99%

Development of EUV lithography tool technologies at Nikon

et al. 2012

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6-mirror-system EUV projection optics design with NA of 0.4 plus was improved and the residual wavefront error was much reduced. Apodization is an issue for such high-NA EUV projection optics. Broad-band multilayer mirror can solve the problem. Broad-band multilayer mirrors were developed. Measured reflectivity performance of these multilayers was in good agreement with the designed performance. We have decided the measures to control contaminations of optics in HVM EUV exposure tools.

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Process liability evaluation for beyond 22nm node using EUVL

Cited by 6 publications

References 0 publications

Application of Extreme Ultraviolet Lithography to Test Chip Fabrication

Application of Extreme Ultraviolet Lithography to Test Chip Fabrication

Study of post-develop defect on typical EUV resist

Development of EUV lithography tool technologies at Nikon

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