Process modeling for sequential build-up of multi-layered structures

Dunne, R.C.; Sitaraman, S.K.

doi:10.1109/ectc.1998.678718

Cited by 12 publications

(13 citation statements)

References 6 publications

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“…Given the nature of residual stresses, caused by encapsulation, and the imperfections caused by handling and processing, backside die cracking is often a major concern [23]. Although it is desirable to use principal stress, the planestrain assumption, particularly under thermal loading, could introduce incorrect out-of-plane ( -direction) stresses and thus could lead to incorrect principal (and also Von Mises) stresses [24]. Therefore, in this study, the magnitude of the axial stress at the backside of the die is used as a representative indicator for possible die cracking.…”

Section: Parametric Studymentioning

confidence: 99%

“…He is a member of the MARC/Center for Board Assembly Research and a member of the Materials Research Council. He was a Symposium Chair in the ASME International Mechanical Engineering Congress and Exposition (IMECE) 1997, was a Technical Chair of IMAPS Packaging Design Workshop 1997, has organized and chaired sessions in ASME- IMECE 1997and 1998, ECTC 1997, 1998and ITHERM 1998, and is on the Program Committee for the ECTC and ITHERM conferences. He also serves as the IMAPS-GT Student Chapter Advisor.…”

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confidence: 99%

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Die cracking and reliable die design for flip-chip assemblies

Michaelides

Sitaraman

1999

IEEE Trans. Adv. Packag.

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Die cracking during underfill cure or thermal cycling is a cause for concern in flip-chip assemblies. In this work, an integrated process-reliability modeling methodology has been developed to determine the stresses at the backside of the die during underfill cure and subsequent thermal cycling. The predicted die stresses have been compared with experimental data, and excellent agreement is seen between the theoretical predictions and the experimental data. The modeling methodology has been used to understand the effect of material and geometry parameters such as substrate thickness, die thickness, standoff height, interconnect pitch, underfill modulus and coefficient of thermal expansion (CTE), and solder mask CTE on die stresses and thus die cracking. Based on underfill-cure and thermal cycling models for specific cases, the critical flaw size to induce catastrophic die cracking has been calculated using linear-elastic fracture mechanics. Design recommendations, including die thinning and polishing, have been made to reduce the tensile stresses on the backside of the die and thus die cracking.

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Section: Parametric Studymentioning

confidence: 99%

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confidence: 99%

Die cracking and reliable die design for flip-chip assemblies

Michaelides

Sitaraman

1999

IEEE Trans. Adv. Packag.

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“…The basic rate equation which expresses the cure reaction rate as a function of time or temperature with conversion is (1) where, is the degree-of-cure (DOC), is the reaction model, is the rate constant, is the pre-exponential or frequency factor, is the activation energy, is the gas constant, is the temperature, is the time, is the exothermic heat of reaction, and is the ultimate heat of the curing reaction [3]. The two reaction models that are used most commonly for thermosetting systems (with chemical-kinetically controlled reactions) are the th order, where , or autocatalytic models, where…”

Section: A Governing Equationsmentioning

confidence: 99%

“…Typically, the HDW structure fabrication process involves the sequential deposition of alternate layers of copper metallization and polymer dielectric on a base substrate, with interconnect vias defined using, for example, photolithographic techniques [1]. Warpage and stresses arise in such multilayered structures during the sequential processing due to the thermal gradients and the Coefficient of Thermal Expansion (CTE) mismatch among the different materials.…”

Section: Introductionmentioning

confidence: 99%

An integrated process modeling methodology and module for sequential multilayered substrate fabrication using a coupled cure-thermal-stress analysis approach

Dunne

Sitaraman

2002

IEEE Trans. Electron. Packag. Manufact.

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An integrated process modeling methodology using a coupled cure-thermal-stress analysis approach has been developed to determine the evolution of warpage and stresses during the sequential fabrication of high-density electronic packaging structures. The process modeling methodology has been demonstrated, for example, with a bi-layer structure consisting of a 3 mil (76. m) thick Vialux 81 photo-definable dry film (PDDF) polymer on a Silicon substrate. Extensive material characterization of the thermo-mechanical properties of the thin film polymer is presented, including the development of a viscoelastic material model. The predicted warpage values have been validated with Shadow Moiré experiments, while the predicted stress values have been validated with experimental data using the Flexus Thin Film Stress Measurement Apparatus. Good agreement is seen between the predicted and the experimental warpage and stressvalues during the entire cure cycle. Finally, the importance of incorporating viscoelastic polymer behavior and processing history is emphasized in the context of developing the multi-layered high-density wiring integrated substrate fabrication process.

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“…Previous approaches to solve this problem were based on the addition of artificial nodes or multipoint constraints [2], [3]. However, we base our strategy in the birth/death of elements capability [4], [5]. The details of the implementation of the modeling approach to take into account the entire history of the fabrication process and a general discussion of the features included in our models will be described in Section II.…”

Section: Introductionmentioning

confidence: 99%

Residual thermomechanical stresses in thinned-chip assemblies

Marco¹,

Beyne²,

Hoof³

et al. 2000

IEEE Trans. Comp. Packag. Technol.

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Abstract-A new technology for the three-dimensional (3-D) stacking of very thin chips on a substrate is currently under development within the ultrathin chip stacking (UTCS) Esprit Project 24910. In this work, we present the first-level UTCS structure and the analysis of the thermomechanical stresses produced by the manufacturing process. Chips are thinned up to 10 or 15 m. We discuss potentially critical points at the edges of the chips, the suppression of delamination problems of the peripheral dielectric matrix and produce a comparative study of several technological choices for the design of metallic interconnect structures. The purpose of these calculations is to give inputs for the definition of design rules for this technology. We have therefore undertaken a programme that analyzes the influence of sundry design parameters and alternative development options. Numerical analyses are based on the finite element method.

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Process modeling for sequential build-up of multi-layered structures

Cited by 12 publications

References 6 publications

Die cracking and reliable die design for flip-chip assemblies

Die cracking and reliable die design for flip-chip assemblies

An integrated process modeling methodology and module for sequential multilayered substrate fabrication using a coupled cure-thermal-stress analysis approach

Residual thermomechanical stresses in thinned-chip assemblies

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