Process Optimization and Downscaling of a Single-Electron Single Dot Memory

Abstract

This paper presents the process optimization of a single-electron nanoflash electron memory. Self-aligned single dot memory structures have been fabricated using a wet anisotropic oxidation of a silicon nanowire. One of the main issue was to clarify the process conditions for the dot formation. Based on the process modeling, the influence of various parameters (oxidation temperature, nanowire shape) has been investigated. The necessity of a sharp compromise between these different parameters to ensure the presence of the memory dot has been established. In order to propose an aggressive memory cell, the downscaling of the device has been carefully studied. Scaling rules show that the size of the original device could be reduced by a factor of 2. This point has been previously confirmed by the realization of single-electron memory devices.Index Terms-Device scaling, flash memories, nonvolatile memories, process modeling, quantum dot, scaling limits, silicon-oninsulator (SOI) technology, single-electron device.

Modelling and engineering of stress based controlled oxidation effects for silicon nanostructure patterning

“…As shown by figure 6(b), the lateral normal stress distribution (σ xx ) is non-uniformly distributed along the vertical direction of the nanobeam. A longer oxidation time tends to enhance this non-uniformity which can explain the formation of a fully separated nanowire/nanotriangular shape surrounded by SiO 2 by only stress effects [13][14][15]. Again, the predicted shape in figure 6(d) is particularly relevant as regards the structure's complexity.…”

“…Self-limited [1][2][3][4][5] or retarded [6] oxidation in silicon nanostructures is an interesting technological tool in order to manipulate the geometrical (shape [7], size [8] and distribution [9]) or the physical properties [1,10,11] of silicon nano-objects. Several applications have been foreseen using this effect such as a nano-field effect transistor [12] and nanoflash memory [13][14][15]. However, the underlying physical mechanisms remain poorly understood at the fundamental level and more knowledge is needed.…”

Energy-Band Engineering for Improved Charge Retention in Fully Self-Aligned Double Floating-Gate Single-Electron Memories

“…In addition, after 50 min, the thicknesses of the three oxide layers become insensitive to the oxidation time. Compared to other anisotropic oxidation processes based on dopant enhancement 21 or pattern conversion, 22 both FGs are progressively separated. These facts indicate that the present process is well controlled thanks to the top nitride layer for protecting oxidation from the top and the Si 0.7 Ge 0.3 layer for enabling a tight control of the different geometrical parameters.…”