Modelling and engineering of stress based controlled oxidation effects for silicon nanostructure patterning

Han, Xiang-Lei; Larrieu, Guilhem; Krzeminski, Christophe

doi:10.1088/0957-4484/24/49/495301

Cited by 18 publications

(30 citation statements)

References 51 publications

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“…Han et al. 31 also reported the fabrication of sub-20 nm Si NPs for VGAA-MOSFETs, but the shape of the reported Si NPs required further improvements.…”

Section: Resultsmentioning

confidence: 99%

Variance Reduction during the Fabrication of Sub-20 nm Si Cylindrical Nanopillars for Vertical Gate-All-Around Metal-Oxide-Semiconductor Field-Effect Transistors

Yamabe

Endoh

2019

ACS Omega

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The variance of sub-20 nm devices is a critical issue for large-scale integrated circuits. In this work, uniform sub-20 nm Si nanopillar (NP) arrays with a reduced diameter variance (to ±0.5 nm) and a cylindrical shape, which can be used for vertical gate-all-around metal-oxide-semiconductor field-effect transistors, were fabricated. For the fabrication process, an array of tapered Si NPs with a diameter of approximately 62.7 nm and a diameter variance of ±2.0 nm was initially fabricated by an argon fluoride lithography followed by dry etching. Then, the NPs were oxidized in a self-limiting region. After the oxide removal, a similar oxidation process was used again for the NPs. It is determined that by controlling oxidation in the self-limiting region, the diameter variance can be reduced in the height direction of Si NPs (as well as shape control) and between NPs, simultaneously with a controllable diameter decrease. This approach decreases the variance in size caused by conventional nanoprocessing and helps overcome the position-dependent variance for 300 mm φ wafers, which is caused by current semiconductor processing.

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“…Han et al. 31 also reported the fabrication of sub-20 nm Si NPs for VGAA-MOSFETs, but the shape of the reported Si NPs required further improvements.…”

Section: Resultsmentioning

confidence: 99%

Variance Reduction during the Fabrication of Sub-20 nm Si Cylindrical Nanopillars for Vertical Gate-All-Around Metal-Oxide-Semiconductor Field-Effect Transistors

Yamabe

Endoh

2019

ACS Omega

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“…We integrated a large ISFET as a reference device together with the 0D ISFET on the same wafer. Although the two transistors were fabricated with identical processes, the oxides are not necessarily identical due to stress effects encountered during oxidation of the nanoscale structure [38][39][40] . When immersed in liquid, the 0D ISFET exhibited a U-shaped pH response, whereas the large ISFET showed the typical pH response for SiO 2 , which was well-described by the SBM (Fig.…”

Section: A 0d Nanotransistor Sensor That Is Chemically Inert To Phmentioning

confidence: 99%

Selective layer-free blood serum ionogram based on ion-specific interactions with a nanotransistor

et al. 2018

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Despite being ubiquitous in the fields of chemistry and biology, the ion-specific effects of electrolytes pose major challenges for researchers. A lack of understanding about ion-specific surface interactions has hampered the development and application of materials for (bio-)chemical sensor applications. Here, we show that scaling a silicon nanotransistor sensor down to ~25 nm provides a unique opportunity to understand and exploit ion-specific surface interactions, yielding a surface that is highly sensitive to cations and inert to pH. The unprecedented sensitivity of these devices to Na and divalent ions can be attributed to an overscreening effect via molecular dynamics. The surface potential of multi-ion solutions is well described by the sum of the electrochemical potentials of each cation, enabling selective measurements of a target ion concentration without requiring a selective organic layer. We use these features to construct a blood serum ionogram for Na, K, Ca and Mg, in an important step towards the development of a versatile, durable and mobile chemical or blood diagnostic tool.

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“…Thermal oxidation is one of the most fundamental processes used for manufacturing nanostructured devices in general and Si NWs in particular, allowing accurate control of the size, surface structure, and electronic properties [6][7][8][9]. Existing experimental studies have shown that the oxidation behavior of silicon nanostructures differs significantly from that of bulk Si [10]. In particular, the oxidation kinetics of Si NWs are found to be surface curvature-and temperature-dependent [11].…”

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confidence: 99%

Two-dimensional modeling of the self-limiting oxidation in silicon and tungsten nanowires

Liu

Jin

et al. 2016

Theoretical and Applied Mechanics Letters

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h i g h l i g h t s• A new diffusion-controlled kinetic model for nanowire oxidation is developed. • A finite reactive region is included to account for oxidation stress and suboxide formation.• Self-limiting nanowire oxidation and its curvature/temperature dependence are predicted. • Results are consistent with observed oxidation behavior of silicon (Si) and tungsten (W) nanowires. a b s t r a c tSelf-limiting oxidation of nanowires has been previously described as a reaction-or diffusion-controlled process. In this letter, the concept of finite reactive region is introduced into a diffusion-controlled model, based upon which a two-dimensional cylindrical kinetics model is developed for the oxidation of silicon nanowires and is extended for tungsten. In the model, diffusivity is affected by the expansive oxidation reaction induced stress. The dependency of the oxidation upon curvature and temperature is modeled. Good agreement between the model predictions and available experimental data is obtained. The developed model serves to quantify the oxidation in two-dimensional nanostructures and is expected to facilitate their fabrication via thermal oxidation techniques.

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Modelling and engineering of stress based controlled oxidation effects for silicon nanostructure patterning

Cited by 18 publications

References 51 publications

Variance Reduction during the Fabrication of Sub-20 nm Si Cylindrical Nanopillars for Vertical Gate-All-Around Metal-Oxide-Semiconductor Field-Effect Transistors

Variance Reduction during the Fabrication of Sub-20 nm Si Cylindrical Nanopillars for Vertical Gate-All-Around Metal-Oxide-Semiconductor Field-Effect Transistors

Selective layer-free blood serum ionogram based on ion-specific interactions with a nanotransistor

Two-dimensional modeling of the self-limiting oxidation in silicon and tungsten nanowires

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