Variance Reduction during the Fabrication of Sub-20 nm Si Cylindrical Nanopillars for Vertical Gate-All-Around Metal-Oxide-Semiconductor Field-Effect Transistors

Abstract

The variance of sub-20 nm devices is a critical issue for large-scale integrated circuits. In this work, uniform sub-20 nm Si nanopillar (NP) arrays with a reduced diameter variance (to ±0.5 nm) and a cylindrical shape, which can be used for vertical gate-all-around metal-oxide-semiconductor field-effect transistors, were fabricated. For the fabrication process, an array of tapered Si NPs with a diameter of approximately 62.7 nm and a diameter variance of ±2.0 nm was initially fabricated by an argon fluoride lithography followed by dry etching. Then, the NPs were oxidized in a self-limiting region. After the oxide removal, a similar oxidation process was used again for the NPs. It is determined that by controlling oxidation in the self-limiting region, the diameter variance can be reduced in the height direction of Si NPs (as well as shape control) and between NPs, simultaneously with a controllable diameter decrease. This approach decreases the variance in size caused by conventional nanoprocessing and helps overcome the position-dependent variance for 300 mm φ wafers, which is caused by current semiconductor processing.

Oxidation of Silicon Nanopillars

“…In this work, the temperatures below (900 °C) and above (1000 °C) the viscous flow limit for SiO 2 are investigated to represent low-temperature and high-temperature thermal oxidation of Si NPs, respectively. Details were introduced elsewhere. ,− …”

“…Multiple Si NPs for each studied diameter were fabricated on a chip for simultaneous oxidation. The NPs had a variation of approximately ±2 nm in diameter prior to oxidation, which can decrease to ±0.5 nm or more through finer controlling of oxidation . Since more than 10 Si NPs in an array could be obtained with each FIB batch (Figure S1), the Si NPs with less variations were compared in this study.…”

“…These features resulted in Si being chosen as the fundamental material for integrated circuits manufactured in the semiconductor industry since the 1960s. The vertical gate-all-around (GAA) structure, − with a gate surrounding a Si nanopillar (NP) or nanowire (NW) channel, exhibits the strongest channel-current controllability available for gate structures of metal-oxide-semiconductor field-effect transistors (MOSFETs). Combined with emerging nonvolatile memory devices, such as spintronic devices, − Si NP-based GAA MOSFETs are expected to be the primary component of the next-generation integrated circuits, according to the International Roadmap for Devices and Systems.…”

“…The authors recently measured the consumed Si at the sidewalls and bottom surface by the change in the NP radius and NP height, respectively. ,− The oxidation at the edge of the surface is found to be slower than that far from the edge oxidized under the same conditions. This is likely because the Si–Si bond has a larger energy barrier to oxidation at an edge, as referred to the edge effect .…”

Controlled Formation of Stacked Si Quantum Dots in Vertical SiGe Nanowires

“…For example, the top Si dot shown in Figure 1F is slightly larger than the middle dot shown in Figure 1G, likely due to the higher oxidation rate at the middle of the pillar when compared with the top or bottom of the pillar. If necessary, it may be possible to mitigate this effect through a multiple-step oxidation in the self-limiting oxidation regime 36,37 such as that done by Ye et al to reduce variations in Si nanopillar oxidation 38 or by placing the Si layers further from the substrate via a deeper RIE. SiGe oxidation is known to occur in a similar fashion to Si oxidation, with the new oxide layer forming at the oxide/SiGe interface.…”