Process simulation of trench gate and plate and trench drain SOI nLDMOS with TCAD tools

Zhang, H.P.; Sun, Lingling; Jiang, Lin; Xu, Liyan; Lin, Mi

doi:10.1109/smelec.2008.4770283

Cited by 4 publications

(1 citation statement)

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“…Thus, it is featured of low on-state voltage drop, low on-state static resistor, and high off-state breakdown voltage. Moreover, it was proved feasible to fabricate in advanced SOI CMOS technologies by 2D TCAD simulation and its channel length could be controlled down to about 130 nm [22]. In order to improve latch-up immunity of SOI LIGBT further, we proposed a vertical gate (VG) RF SOI LIGBT structure based on all the achievements above as illustrated in Figure 7.…”

Section: Our Researches On Vertical Gate Soi Ldmos/ligbtmentioning

confidence: 99%

Vertical Gate RF SOI LIGBT for SPICs with Significantly Improved Latch-Up Immunity

Zhang

et al. 2011

VLSI Design

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Based on the previous achievements in improving latch-up immunity of SOI LIGBT, process simulation on our proposed VG RF SOI NLIGBT was carried out with TCAD to provide a virtually fabricated device structure. Then, an approximate latching current model was derived according to the condition of minimum regenerative feedback couple between the parasitic dualtransistors. The model indicates that its latching current is a few orders higher than those before. Further verification through device simulation was done with TCAD, which proved that its weak snapback voltage in the off state is about 0.5-2.75 times higher than those breakdown voltages reported before, its breakdown voltage in the off state is about 19 V higher than its weak snapback voltage, and its latching current density in the on state is about 2-3 orders of magnitude higher than those reported before at room temperature due to hole current bypass through P + contact in P-well region. Therefore, it is characterized by significantly improved latch-up immunity.

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Section: Our Researches On Vertical Gate Soi Ldmos/ligbtmentioning

confidence: 99%