Process variation aware cache leakage management

Meng, Ke; Joseph, Russ

doi:10.1145/1165573.1165636

Cited by 41 publications

(12 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Most efforts dealing with variation have focused on mitigating and exploiting it in processors [6], [7], [11], [12] or in on-chip memory [13], [14], [15], [16], [17]. Fewer papers have looked at variability in off-chip, DRAM-based memory subsystems.…”

Section: Related Workmentioning

confidence: 99%

ViPZonE: Hardware Power Variability-Aware Virtual Memory Management for Energy Savings

Gottscho

Bathen

Dutt

et al. 2015

IEEE Trans. Comput.

View full text Add to dashboard Cite

Abstract-Hardware variability is predicted to increase dramatically over the coming years as a consequence of continued technology scaling. In this paper, we apply the Underdesigned and Opportunistic Computing (UnO) paradigm by exposing system-level power variability to software to improve energy efficiency. We present ViPZonE, a memory management solution in conjunction with application annotations that opportunistically performs memory allocations to reduce DRAM energy. ViPZonE's components consist of a physical address space with DIMM-aware zones, a modified page allocation routine, and a new virtual memory system call for dynamic allocations from userspace. We implemented ViPZonE in the Linux kernel with GLIBC API support, running on a real x86-64 testbed with significant access power variation in its DDR3 DIMMs. We demonstrate that on our testbed, ViPZonE can save up to 27.80 percent memory energy, with no more than 4.80 percent performance degradation across a set of PARSEC benchmarks tested with respect to the baseline Linux software. Furthermore, through a hypothetical "what-if" extension, we predict that in future non-volatile memory systems which consume almost no idle power, ViPZonE could yield even greater benefits, demonstrating the ability to exploit memory hardware variability through opportunistic software.

show abstract

Section: Related Workmentioning

confidence: 99%

ViPZonE: Hardware Power Variability-Aware Virtual Memory Management for Energy Savings

Gottscho

Bathen

Dutt

et al. 2015

IEEE Trans. Comput.

View full text Add to dashboard Cite

show abstract

“…To obtain a smaller switching delay, the threshold voltage for the transistor must be decreased. Unfortunately, subthreshold leakage current increases exponentially as threshold voltage decreases [13,8]. This suggests modeling the speed to power function as something like P (s) = s α + c, where there is some range of speeds [s min , s max ] that the processor can run at.…”

Section: Technological Motivationsmentioning

confidence: 99%

Speed Scaling with an Arbitrary Power Function

Bansal

Chan

Pruhs

2013

ACM Trans. Algorithms

View full text Add to dashboard Cite

"What matters most to the computer designers at Google is not speed, but power, low power, because data centers can consume as much electricity as a city." -Dr. Eric Schmidt, CEO of Google [12]. AbstractAll of the theoretical speed scaling research to date has assumed that the power function, which expresses the power consumption P as a function of the processor speed s, is of the form P = s α , where α > 1 is some constant. Motivated in part by technological advances, we initiate a study of speed scaling with arbitrary power functions. We consider the problem of minimizing the total flow plus energy. Our main result is a (3+ǫ)-competitive algorithm for this problem, that holds for essentially any power function. We also give a (2+ǫ)-competitive algorithm for the objective of fractional weighted flow plus energy. Even for power functions of the form s α , it was not previously known how to obtain competitiveness independent of α for these problems. We also introduce a model of allowable speeds that generalizes all known models in the literature.

show abstract

“…The decrease of feature size introduces random process changes which mainly come from pollution, environmental variation and high temperature [28]. It brings the variation of IC physical structure and degradation of the circuit performance.…”

Section: Trend Of Interconnect Processmentioning

confidence: 99%

Review of the Global Trend of Interconnect Reliability for Integrated Circuit

Lin¹,

Wu²,

Jia³

2018

View full text Add to dashboard Cite

Interconnect reliability has been regarded as a discipline that must be seriously taken into account from the early design phase of integrated circuit (IC). In order to study the status and trend of the interconnect reliability, a comprehensive review of the published literatures is carried out. This can depict the global trend of ICs' interconnect reliability and help the new entrants to understand the present situation of this area.

show abstract

Process variation aware cache leakage management

Cited by 41 publications

References 18 publications

ViPZonE: Hardware Power Variability-Aware Virtual Memory Management for Energy Savings

ViPZonE: Hardware Power Variability-Aware Virtual Memory Management for Energy Savings

Speed Scaling with an Arbitrary Power Function

Review of the Global Trend of Interconnect Reliability for Integrated Circuit

Contact Info

Product

Resources

About