Process variation compensation of a 4.6 GHz LNA in 65nm CMOS

Abstract

We present the design of a 4.6 GHz LNA in TSMC 65nm with a feedback scheme to compensate for variations across process, supply voltage, and temperature. No post fabrication efforts are required in this compensation method. The proposed method improves the variation in S 21 of an inductively degenerated cascode LNA from 8.75% to 1.27%, which is a reduction in variation of 85%. The presented scheme is also robust over variations in supply voltage, temperature, and process conditions. The compensation method presented can be utilized to stabilize the gain of a wide variety of amplifiers.

Common‐rail powered reliability improving technique for single‐supply complementary metal oxide semiconductor amplifiers

“…For the RIC, maximum improvement in variability is obtained for peak gain (up to 16.7%) against a varying supply and reduction in gain deviation against VPC and VTV is up to 8.3 and 12.3%, respectively. Therefore the RIC will increase the constancy of a front-end's gain profiles and is more effective in stabilising gain than [22,25] are able to improve gain fluctuation by < 2.5 and < 4.1% against alteration of device threshold and supply voltage. The references are selected to focus on similar circuit architectures (CMOS amplifiers) with [19] stabilitating a class AB power amplifier and [22] improving a cascode amplifier.…”

“…The references are selected to focus on similar circuit architectures (CMOS amplifiers) with [19] stabilitating a class AB power amplifier and [22] improving a cascode amplifier. Compensation circuits for LNAs are proposed in [23][24][25] with the help of features like switchable capacitance, reconfigurability and feedback schemes. The techniques of [19,24] achieve best results for varying process corners and the mechanism of [25] works against supply deviation.…”

“…Compensation circuits for LNAs are proposed in [23][24][25] with the help of features like switchable capacitance, reconfigurability and feedback schemes. The techniques of [19,24] achieve best results for varying process corners and the mechanism of [25] works against supply deviation. The scheme of [22] has a more prominent effect on NF variability and its gain regulation is less effective.…”

“…The objective of including a reliability improving circuit (RIC) in a CMOS architecture is to reduce variation in the system's figures of merit (FOM). Recent literature has addressed this issue for various radio frequency (RF), digital and digital-to-analog-conversion (DAC) circuits [5,[16][17][18][19][20][21][22][23][24][25][26][27][28][29]. For example, a reliability-sensitive power amplifier is presented in [5] which can be integrated with a wireless fidelity receiver to mitigate discharge/aging issues.…”

“…A self-healing front-end is developed in [24] using a reconfigurable architecture against varying process factors. The capacity of a feedback network to stabilitate gain is manifested in [25] for a 5 GHz amplifier. To achieve the same effect, a bias compensation technique is presented in [26] for a wideband code division multiple access amplifier.…”