Process variation compensation with effective gate-width tuning for low-voltage CMOS digital circuits

Kishiwada, Yasushi; Ueda, Shun; Miyawaki, Yusuke; Matusoka, Toshimasa

doi:10.1109/imfedk.2012.6218634

Cited by 4 publications

(3 citation statements)

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“…2 (d). The temperature dependence of the operation speed in the CMOS logic circuits can be reduced with the proposed technique, as shown in previous work [5]; however, it is not so important in this work because the solution temperature is nearly constant for stable DEP operation.…”

Section: Effective Gate-width Tuningmentioning

confidence: 68%

“…The body biasing used in previous work [6,7,8] is such a technique; however, at 0.35 V it cannot function sufficiently due to limited body biases. Therefore, we developed an additional process variation compensation technique with effective gate-width tuning [5].…”

Section: System Designmentioning

confidence: 99%

“…It is also useful to reduce the output of the wireless power transmitter. Therefore, we investigated on-chip microparticle manipulation under a low supply voltage and frequency using process variation compensation with effective gate-width tuning [5], as well as body biasing based on previous work [6,7,8]. Figure 1 shows the proposed wireless on-chip microparticle manipulation system.…”

Section: Introductionmentioning

confidence: 99%

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Low-power wireless on-chip microparticle manipulation with process variation compensation

Kishiwada

Iwasaki

Ueda

et al. 2013

IEICE Electron. Express

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Abstract:A chip with which to manipulate microparticles using wireless power transfer and pulse-driven dielectrophoresis has been designed and fabricated using a 0.18-μm CMOS process. The chip enables microparticle manipulation using a 0.35-V power supply and a 10∼100 kHz clock, which are generated on the chip by means of an onchip coil, a rectifier and a ring oscillator circuit with process variation compensation circuits. The proposed process variation compensation with effective gate-width tuning as well as body biasing can achieve stable 0.35-V operation, allowing a 87% reduction in the power consumption of digital circuits on the chip compared to previous work.

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Section: Effective Gate-width Tuningmentioning

confidence: 68%