Process Variation Tolerant Pipeline Design Through a Placement-Aware Multiple Voltage Island Design Style

Stefano,; Bertozzi,; Benini, Luca; Macii,

doi:10.1109/date.2008.4484806

Cited by 11 publications

(11 citation statements)

References 16 publications

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“…There are also several techniques on higher abstraction levels including Razor [14] and its variants [25] which aim at achieving energyperformance optimum under process variations. A further highlevel variation-aware design approach is reported in [42]. All these statistical design methods tend to prevent or conceal corner-case situations when the circuit operates very close to or beyond its specifications.…”

Section: A Variation-aware Designmentioning

confidence: 99%

Towards Variation-Aware Test Methods

Polian

Becker

Hellebrand

et al. 2011

2011 Sixteenth IEEE European Test Symposium

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Nanoelectronic circuits are increasingly affected by massive statistical process variations, leading to a paradigm shift in both design and test area. In circuit and system design, a broad class of methods for robustness like statistical design and self calibration has emerged and is increasingly used by the industry. The test community's answer to the massive-variation challenge is currently adaptive test. The test stimuli are modified on the fly (during test application) based on the circuit responses observed. The collected circuit outputs undergo statistical post-processing to facilitate pass/fail classification. We will present fundamentals of adaptive and robust test techniques and their theoretical background. While adaptive test is effective, the understanding how it covers defects under different process parameter combinations is not fully established yet with respect to algorithmic foundations. For this reason, novel analytic and algorithmic approaches in the field of variation-aware testing will also be presented in the tutorial. Coverage of defects in the process parameter space is modeled and maximized by an interplay between special fault simulation and multi-constrained ATPG algorithms. These systematic approaches can complement adaptive test application schemes to form a closed-loop system that combines analytical data with measurement results for maximal test quality. Preprint General Copyright NoticeThis article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, re-distribution, re-selling, loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden. This is the author's "personal copy" of the final, accepted version of the paper published by IEEE.

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Section: A Variation-aware Designmentioning

confidence: 99%

Towards Variation-Aware Test Methods

Polian

Becker

Hellebrand

et al. 2011

2011 Sixteenth IEEE European Test Symposium

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show abstract

“…On the other hand, process variations have led to a paradigm shift in design methods towards what is known as statistical design [6], as well as to the development of novel, variation-tolerant architectures [7]. However, variation-aware testing is particularly challenging.…”

Section: Introductionmentioning

confidence: 99%

Variation-aware fault modeling

Hopsch

Becker

Hellebrand

et al. 2011

Sci. China Inf. Sci.

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To achieve a high product quality for nano-scale systems, both realistic defect mechanisms and process variations must be taken into account. While existing approaches for variation-aware digital testing either restrict themselves to special classes of defects or assume given probability distributions to model variabilities, the proposed approach combines defect-oriented testing with statistical library characterization. It uses Monte Carlo simulations at electrical level to extract delay distributions of cells in the presence of defects and for the defect-free case. This allows distinguishing the effects of process variations on the cell delay from defectinduced cell delays under process variations. To provide a suitable interface for test algorithms at higher levels of abstraction, the distributions are represented as histograms and stored in a histogram data base (HDB). Thus, the computationally expensive defect analysis needs to be performed only once as a preprocessing step for library characterization, and statistical test algorithms do not require any low level information beyond the HDB. The generation of the HDB is demonstrated for primitive cells in 45 nm technology. Preprint General Copyright NoticeThis article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, re-distribution, re-selling, loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden. This is the author's "personal copy" of the final, accepted version of the paper published by Science China Press and Springer-Verlag Berlin Heidelberg. 1 Fraunhofer IIS/EAS, Dresden D-010169,G e r m a n y 2 University of Freiburg, Freiburg D-79110,G e r m a n y 3 University of Paderborn, Paderborn D-33098,G e r m a n y 4 University of Passau, Passau D-94023,G e r m a n y 5 University of Stuttgart, Stuttgart D-70569,G e r m a n y Received March 21, 2011; accepted June 21, 2011Abstract To achieve a high product quality for nano-scale systems, both realistic defect mechanisms and process variations must be taken into account. While existing approaches for variation-aware digital testing either restrict themselves to special classes of defects or assume given probability distributions to model variabilities, the proposed approach combines defect-oriented testing with statistical library characterization. It uses Monte Carlo simulations at electrical level to extract delay distributions of cells in the presence of defects and for the defect-free case. This allows distinguishing the effects of process variations on the cell delay from defectinduced cell delays under process variations. To provide a suitable interface for test algorithms at higher levels of abstraction, the distributions are represented as histograms and stored in a histogram data base (HDB). Thus, the computationally expensive defect analysis needs to be performed only once as a preprocessing step for library characterization, and statistical test algorithms do not require any low level i...

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“…That is, it is not enough to know the percentage of variation but it is required to analyze how each particular device suffers from it depending on its size. This is an improvement over other variability models previously proposed [92] [36] [97]. Therefore, to compute σ V th for a given device, according to [2], we use Equation 3.5, and then relate the σ V th 0 value of the minimum size device with the σ V th of a device of size h, as shown in Equation 3.6, which clearly shows that σ V th can be minimized by increasing the width of devices, represented by h. However, this would increase the area required to implement the circuit as well as the power consumption, which is not a good option.…”

Section: Modeling Random Threshold Voltage Variationmentioning

confidence: 86%

“…On the other hand, variability can be either compensated or tolerated. For example, [75,97] propose to design for the typical case and perform post-silicon compensation at some cost (performance, power). In [22,64] delay failures are tolerated at the cost of performance.…”

Section: Related Workmentioning

confidence: 99%

“…al [8]. Later, variability models that characterize variations in microarchitecture have been deployed [92] [42] [97] allowing designers to analyze the consequences of parameter variation in processor architectures. However, these studies focus on the impact of within-die variations in the processor architecture, not considering the implications of variations in the interconnect infrastructure.…”

Section: Related Workmentioning

confidence: 99%

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Addressing Manufacturing Challenges in NoC-based ULSI Designs

Luz¹

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ii AgradecimientosVarios han sido los años de mi vida que he dedicado a la realización de esta tesis. Durante estos años si bien he conseguido compaginar mi vida personal con el desarrollo de la la tesis, ha sido el doctorado el que ha marcado de algún modo u otro los tiempos en mi vida. Por todo esto y por mucho más agradezco a Anna la paciencia que durante todos estos años me ha mostrado. Sin su cariño y comprensión la realización de la tesis hubiera sido sin duda un proceso mucho más tortuoso. También aprovecho para agradecer a mis padres que en todo momento me incentivaran a llegar siempre lo más lejos posible en la formación académica. En numerosas ocasiones a lo largo de la tesis me he preguntado si todo esto realmente vale la pena. Ahora con perspectiva y la tesis bajo el brazo todo se ve distinto.Por otro lado me gustaría agradecer a Federico Silla, Vicente Santonja y José Duato la oportunidad que me brindaron para realizar el doctorado en Informática en el Grupo de Arquitecturas Paralelas. Quisiera agradecer especialmente a Fede la ayuda que me ha prestado durante estos años y que ha sido fundamental para la realización de la tesis.Aunque una tesis supone un importante sacrificio personal, no hay que obviar que para la realización de la misma he contado con la inestimable ayuda de muchos compañeros de laboratorio. Durante la etapa inicial de mi doctorado fueron Ricardo, Blas, Crispin, Gaspar, Andres, Paco, Hector, Rafa, David y Noel mis compañeros en el GAP. Con ellos he compartido buenos momentos dentro y fuera del laboratorio. Recuerdo con especial cariño las innumerables ocasiones en las que Hector y yo ( al principio con la compañía de David) maldijimos el día en el que decidimos hacer la tesis. Cinco años después esta etapa ha acabado y una nueva empieza en Barcelona. Más tarde iii iv la incorporación de Toni, con el que ya compartí buenos momentos en los trabajos de Microelectrónica de Teleco, ha sido un apoyo fundamental a la hora de afrontar los problemas que desde el lado oscuro, en el cual mi tesis se ha desarrollado, han ido surgiendo. Finalmente nuevos compañeros de laboratorio como Javi, Knut, Mario, Alberto... han hecho posible que el ambiente del laboratorio siga tan bueno como siempre.Porúltimo no podía olvidarme de agradecer a mis amigos; a los que son heavies y a los que son flamencos, a los que disfrutan de la escalada y a los playeros, a los de la facultad y a los que no han estudiado, que hayan hecho que el tiempo que ha durado la tesis pase tan rápido. Sin duda he disfrutado mucho durante todo este tiempo.

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Process Variation Tolerant Pipeline Design Through a Placement-Aware Multiple Voltage Island Design Style

Cited by 11 publications

References 16 publications

Towards Variation-Aware Test Methods

Towards Variation-Aware Test Methods

Variation-aware fault modeling

Addressing Manufacturing Challenges in NoC-based ULSI Designs

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