Processing Near Sensor Architecture in Mixed-Signal Domain With CMOS Image Sensor of Convolutional-Kernel-Readout Method

Tang

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

et al. 2021

Self Cite

In the era of Intelligent IoT, huge amount of sensor data is collected and then transmitted to processor elements in edge devices or cloud servers. The latency and energy consumption in this process have been a bottleneck and are becoming more severe. To mitigate this problem, the idea of combining sensors, memory and processors for collectively handling the data, has been proposed and explored actively in recent efforts. In this work, thin-film transistor (TFT), which has been widely adopted in display devices and flexible sensors, is exploited. It is shown that, while TFT is promising for nearsensor processing architecture, it also shows a great potential for computing and storage for large-area and low-cost edge sensors. More specifically, we propose an almost-nonvolatile near-sensor computing-in-memory (CiM) array based on indium-galliumzinc-oxide (IGZO) TFT, and further, integrate the CiM array with a sensor array to be a sensing and data pre-process system. We show that such a TFT-based solution can accomplish realtime sensing and multiply-and-accumulate (MAC) processing in the analog field, which simplifies the system design with lowered energy and latency in our neural network evaluations.

Section: Tft Near-sensor Cim Systemmentioning

confidence: 99%

Almost-Nonvolatile IGZO-TFT-Based Near-Sensor In-Memory Computing

Tang

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

et al. 2021

Self Cite

“…D EEP neural networks (DNNs) have been powering a broad range of applications [3], [4], [5], [6], [7], including natural language processing, image classification, and object recognition. The demand to achieve high accuracy for increasingly computational tasks leads to ever-growing model sizes of modern DNNs [8], [9].…”

Section: Introductionmentioning

confidence: 99%

Neural-PIM: Efficient Processing-In-Memory with Neural Approximation of Peripherals

Cao,

Zhao,

Boloor

et al. 2022

Preprint

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Processing-in-memory (PIM) architectures have demonstrated great potential in accelerating numerous deep learning tasks. Particularly, resistive random-access memory (RRAM) devices provide a promising hardware substrate to build PIM accelerators due to their abilities to realize efficient in-situ vector-matrix multiplications (VMMs). However, existing PIM accelerators suffer from frequent and energy-intensive analog-to-digital (A/D) conversions, severely limiting their performance. This paper presents a new PIM architecture to efficiently accelerate deep learning tasks by minimizing the required A/D conversions with analog accumulation and neural approximated peripheral circuits. We first characterize the different dataflows employed by existing PIM accelerators, based on which a new dataflow is proposed to remarkably reduce the required A/D conversions for VMMs by extending shift and add (S+A) operations into the analog domain before the final quantizations. We then leverage a neural approximation method to design both analog accumulation circuits (S+A) and quantization circuits (ADCs) with RRAM crossbar arrays in a highly-efficient manner. Finally, we apply them to build a RRAMbased PIM accelerator (i.e., Neural-PIM) upon the proposed analog dataflow and evaluate its system-level performance. Evaluations on different benchmarks demonstrate that Neural-PIM can improve energy efficiency by 5.36× (1.73×) and speed up throughput by 3.43× (1.59×) without losing accuracy, compared to the state-of-the-art RRAM-based PIM accelerators, i.e., ISAAC [1] (CASCADE [2]).

“…The absence of data format converters allows us to reduce the hardware cost. A frequently used option is near-sensor calculation in the analog form [2,3]. Another option is pulse form calculations, since the conversion of analog signals into pulse time parameters is not complicated.…”

Section: Introductionmentioning

confidence: 99%

Bit Streaming Processing Algorithms for Intelligent Hardware Converters

2021

The need to transfer the primary data conversions close to the sensors, to the endpoints of monitoring systems, as well as in IoT terminal devices makes the development of new approaches to computing and the design of appropriate algorithms relevant. The article shows stream processing algorithms that provide functional transformations of signals presented in bit stream form (single pulse streams, PWM signal streams) and binary codes at the same time. In such algorithms, the computational process is based on discretization, pulse frequency sweep and pulse-width sweep of codes as well as organization of parallel-serial processing. The suggested principles of algorithm organization are based on the fact that the computation is considered not as an event associated with calculation but as a continuous process of a result formation. The transition to algorithmic representations proposed by the authors makes it possible to obtain universal behavioral descriptions, independently of the specific hardware on which their implementation is performed.