Processing of ultrathin 300 mm wafers with carrierless technology

Spiller, Sven; Molina, Froilan; Wolf, J.K.; Grafe, Juergen; Schenke, Andreas; Toennies, Dietrich; Hennemeyer, Marc; Tabuchi, Tomotaka; Auer, Hans

doi:10.1109/ectc.2011.5898629

Cited by 6 publications

(4 citation statements)

References 6 publications

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“…While the aforementioned methods all require a sort of carrier to handle the UTS, TAIKO method is carrier-free since it leaves the peripheral ring unaffected when grinding such that the ring is utilized to handle the UTS. [18,19] In this paper, we explore the fabrication potential of the doublesided process that relies on the self-delamination based "pattern transfer" technique. [1] While the previous paper introduced this technique involving material deposition on the backside, it did not demonstrate subsequent material patterning.…”

Section: Introductionmentioning

confidence: 99%

“…While the aforementioned methods all require a sort of carrier to handle the UTS, TAIKO method is carrier‐free since it leaves the peripheral ring unaffected when grinding such that the ring is utilized to handle the UTS. [ 18,19 ]…”

Section: Introductionmentioning

confidence: 99%

“…[14,15] However, the warpage or deflection induced by high stress can be a problem while subsequential handling and processing. Therefore techniques such as Dicing-Before-Grinding (DBG) [16,17] and TAIKO [18,19] are used to avoid the downside of the grinding method. Moreover, dry etching such as reactive ion etching, [20,21] or XeF 2 etching [22] can also be used to get UTS.…”

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confidence: 99%

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Dual Coil Patterned Ultra‐Thin Silicon Film Enable by Double‐Sided Process

Son

Lee

Ferreira

et al. 2023

Adv Materials Inter

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Double‐sided microfabrication process on an ultra‐thin silicon film has rarely been attempted due to the challenges in terms of the preparation and handling of a thin film in spite of its promising fabrication potentials. Such a process allows for doubling the thin film device density or providing dual functionalities for a thin film depending on whether the front and back sides of a thin film are processed identically or distinctively. Here, a novel double‐sided thin film processing strategy is introduced by realizing a dual coil patterned ultra‐thin silicon film that is working as an actuating or energy harvesting system. Experimentally, a dual coil patterned thin film enabled using the introduced approach shows remarkably enhanced device performance when compared with a single coil patterned counterpart. Furthermore, a multiphysics simulation model is developed and the resultant modeling data validate the experimentally measured performance enhancement. Finally, the structural durability of the thin film upon cyclic loading is tested and its diverse vibration modes are investigated.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

mentioning

confidence: 99%

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Dual Coil Patterned Ultra‐Thin Silicon Film Enable by Double‐Sided Process

Son

Lee

Ferreira

et al. 2023

Adv Materials Inter

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“…Carrierless technology provides a low cost solution because the temporary bonding and de-bonding process are not needed. A 300 mm wafer with the thickness of 150 μm is demonstrated but it needs more study for thinner wafers [3]. In this research, thin wafer handling system with carrier wafer is focused.…”

Section: Introductionmentioning

confidence: 99%

Thin wafer handling process evaluation for 3DIC integration

Chang

Tsai

Chien

et al. 2012

2012 7th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT)

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After temporary bonding and thinning process, many backside processes will be conducted on the thinned wafer. The critical processes for thin wafer handling material are high temperature and high vacuum processes. In this article, a quick adhesive selecting method is proposed. Backside process of PECVD SiO 2 is identified as the most critical process for thin wafer handling material selection. Two thermal plastic thin wafer handling materials are used in this study for 300 mm wafers and thermal compress bonding in a vacuum chamber is used for bonding process. After bonding, the wafer is thinned down to 50 μm by a commercialized grinder and the PECVD SiO 2 process is conducted on the thinned wafer. Many dishes were found after PECVD SiO 2 process because there is outgassing from the thin wafer handling material or from the device/carrier wafer surface. In this research, an additional hold time is proposed to reduce the dishing after PECVD SiO 2 process. Different hold time at 210 ℃ and different bonding time are evaluated. For the bonding process without hold time, large voids are observed. There are also 29 dishes on the surface of the wafer. By adding additional 5 minutes hold time before bonding, the number of the dishing on the wafer surface reduced from 29 to 6. If the hold time is set to 10 minutes, only 4 dishes were found on the wafer surface. From the evaluation result of these two thermal plastic thin wafer handling materials, B-glue seems much better than A-glue. The hold time seems very critical on void reduction during bonding process. From B-glue on PECVD SiO 2 experiment, 10 minutes hold time has the better performance for void reduction. The bonding process with zero hold time has the worst performance which has many voids after PECVD SiO 2 process. An ultra-thin 300 mm wafer with a thickness less than 7 μm is also demonstrated in this research by using B-glue and 10 minutes hold time.

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Double‐sided transistor device processability of carrierless ultrathin silicon wafers

Lai

Hymel

Liu

et al. 2020

InfoMat

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Double‐sided metal‐oxide‐semiconductor field‐effect‐transistor processing is demonstrated for the first time on an ultrathin crystalline silicon substrate of 6‐20 μm in a 100 mm diameter wafer format without a carrier wafer, the thinnest free‐standing silicon wafers ever fabricated. The compatibility of the flexible material with conventional semiconductor processing tools is enabled by supporting an interior ultrathin silicon with a surrounding thicker ring of silicon. Current‐voltage characteristics of transistors on ultrathin silicon show performance as expected from bulk silicon, with electron mobility ~1500 cm2 V−1 second−1. Mechanical measurements quantify the handleability.image

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Processing of ultrathin 300 mm wafers with carrierless technology

Cited by 6 publications

References 6 publications

Dual Coil Patterned Ultra‐Thin Silicon Film Enable by Double‐Sided Process

Dual Coil Patterned Ultra‐Thin Silicon Film Enable by Double‐Sided Process

Thin wafer handling process evaluation for 3DIC integration

Double‐sided transistor device processability of carrierless ultrathin silicon wafers

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