A common requirement for all current and future TSV (Through Silicon Via) applications is the ability to handle and process thinned Silicon Wafers, usually in the range of 150m or much below. Silicon Wafers of this thickness cannot be handled without support as wafers with the standard thickness. One solution to tackle this problem is the use of wafer-support-systems (WSS), in which the thinned wafers are bonded temporarily to a carrier wafer, which gives the wafer mechanical stability. Another solution for handling are carrierless systems, in which the wafer is modified in a way that it is thin and mechanically rigid at the same time. Existing carrierless systems provide mechanical integrity for the wafer, but lack the full integration into backside processing. In this paper, we present a carrierless approach that provides mechanical stability and can be integrated into backside processing technology at the same time. We present results of a carrierless wafer with a th ickness of 60m only which has undergone a bumping process at the backside

We present a "carrierless" design for the manufacturing of ultrathin Silicon wafers, which are used in e.g. TSV (Through Silicon Via) and power chip applications. A carrierless wafer is a wafer which has a thinned inner portion, usually thinner than 150 m, and a rim portion, which is stabilizing the wafer, so that the whole wafer can be handled without any additional support. In more detail, progress on 300 mm carrierless wafers and its compatibility with standard applications like RDL (Redistribution Layer) and bumping will be discussed

This paper presents a new carrierless approach to handling and processing ultra-thin Silicon which is predominantly used in processing Through Silicon Via (TSV) wafers. Currently, the state of the art consists of bonding the wafers having the vias onto a carrier wafer, after which the thinning steps of the wafer and the backside processing, e.g. Redistribution (RDL) or Bumping, are performed. By means of temporarily bonding the wafer to a carrier, the wafer has structural integrity and can be handled and processed at standard equipment. An alternative to the carrier approach is the use of carrierless ultra thin wafers. Here, the wafer is modified mechanically in a way that the wafer is thin and rigid at the same time. This approach has the potential of bypassing the bonding and de-bonding operations. In detail, we will present results on: 200 mm backside processing 200 mm "Via Reveal" process 300 mm mechanical stability Special lithography process for carrierless wafers