Profile-directed restructuring of operating system code

Schmidt, William J.; Roediger, Robert R.; Mestad, C. S.; Mendelson, Bilha; Shavit-Lottem, I.; Bortnikov-Sitnitsky, V.

doi:10.1147/sj.372.0270

Cited by 24 publications

(10 citation statements)

References 22 publications

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“…Much research focuses on improving the Pettis and Hanson methodology to include cache line coloring to reduce conflict misses [Aydin and Kaeli 2000;Hashemi et al 1997;Kaeli 1999, 2000] by placing popular procedures in the memory such that the number of overlapping cache lines in minimized. Also, various production tools offer Pettis and Hanson-based code reordering as an optimization option such as Compaq's Object Modification Tool (OM) [Srivastava and Wall 1992], its successor Spike [Cohn et al 1997], and IBM's FDPR [Schmidt et al 1998]. Other works provide methodologies for applying code reordering to commercial applications [Ramirez et al 2002].…”

Section: Non-cache-aware Code Reordering Background and Code Reorderimentioning

confidence: 99%

Combining code reordering and cache configuration

Gordon‐Ross

Vahid

Dutt

2012

ACM Trans. Embed. Comput. Syst.

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The instruction cache is a popular optimization target due to the cache's high impact on system performance and power and because of the cache's predictable temporal and spatial locality. This article is an in depth study on the interaction of code reordering (a long-known technique) and cache configuration (a relatively new technique). Experimental results show that code reordering coupled with cache configuration reveals additional energy savings as high as 10-15% for several benchmarks with reduced cache area as high as 48%. To exploit these additional benefits, we architect and evaluate several design exploration heuristics for combining these two methods.

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Section: Non-cache-aware Code Reordering Background and Code Reorderimentioning

confidence: 99%

Combining code reordering and cache configuration

Gordon‐Ross

Vahid

Dutt

2012

ACM Trans. Embed. Comput. Syst.

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“…To detect kernel bottlenecks, profile information is used. Profile-guided restructuring of the operating system for the optimization of its throughput or latency has been studied for AS400 [Schmidt et al 1998] and HP-UX [Speer et al 1994] platforms.…”

Section: Other Operating System Kernel Optimization Approachesmentioning

confidence: 99%

Automated reduction of the memory footprint of the Linux kernel

Chanet

Sutter

Bus

et al. 2007

ACM Trans. Embed. Comput. Syst.

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The limited built-in configurability of Linux can lead to expensive code size overhead when it is used in the embedded market. To overcome this problem, we propose the application of link-time compaction and specialization techniques that exploit the a priori known, fixed runtime environment of many embedded systems. In experimental setups based on the ARM XScale and i386 platforms, the proposed techniques are able to reduce the kernel memory footprint with over 16%. We also show how relatively simple additions to existing binary rewriters can implement the proposed techniques for a complex, very unconventional program, such as the Linux kernel. We note that even after specialization, a lot of seemingly unnecessary code remains in the kernel and propose to reduce the footprint of this code by applying code-compression techniques. This technique, combined with the previous ones, reduces the memory footprint with over 23% for the i386 platform and 28% for the ARM platform. Finally, we pinpoint an important code size growth problem when compaction and compression techniques are combined on the ARM platform

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“…A solution to this problem is to co-allocate hot method tables to ensure that they occupy a small number of pages to achieve higher utilization of TLB entries. Co-allocation of hot method tables can be done at GC time by combining the techniques reported in [ 12] and [36].…”

Section: Sources Of Data Tlb Missesmentioning

confidence: 99%

Characterizing the memory behavior of Java workloads

Shuf

Serrano

Gupta

et al. 2001

Proceedings of the 2001 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems

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This paper studies the memory behavior of important Java workloads used in benchmarking Java Virtual Machines (JVMs), based on instrumentation of both application and library code in a state-of-theart JVM, and provides structured information about these workloads to help guide systems' design. We begin by characterizing the inherent memory behavior of the benchmarks, such as information on the breakup of heap accesses among different categories and on the hotness of references to fields and methods. We then provide detailed information about misses in the data TLB and caches,including the distribution of misses over different kinds of accesses and over different methods. In the process, we make interesting discoveries about TLB behavior and limitations of data prefetching schemes discussed in the literature in dealing with pointer-intensive Java codes. Throughout this paper, we develop a set of recommendations to computer architects and compiler writers on how to optimize computer systems and system software to run Java programs more efficiently. This paper also makes the first attempt to compare the characteristics of SPECjvm98 to those of a server-oriented benchmark, pBOB, and explain why the current set of SPECjvm98 benchmarks may not be adequate for a comprehensive and objective evaluation of JVMs and just-in-time (JIT) compilers.We discover that the fraction of accesses to array elements is quite significant, demonstrate that the number of "hot spots" in the benchmarks is small, and show that field reordering cannot yield significant performance gains. We also show that even a fairly large L2 data cache is not effective for many Java benchmarks. We observe that instructions used to prefetch data into the L2 data cache are often squashed because of high TLB miss rates and because the TLB does not usually have the translation information needed to prefetch the data into the L2 data cache. We also find that co-allocation of frequently used method tables can reduce the number of TLB misses and lower the cost of accessing type information block entries in virtual method calls and runtime type checking.

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Profile-directed restructuring of operating system code

Cited by 24 publications

References 22 publications

Combining code reordering and cache configuration

Combining code reordering and cache configuration

Automated reduction of the memory footprint of the Linux kernel

Characterizing the memory behavior of Java workloads

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