Profile engineering for sub-micron CMOS using high energy ion implantation

Abstract

An improved implantation scheme has been developed for a sub micron retrograde twin-well CMOS process. A blanket p-well im plantation is used to avoid one photoresist step. The use of a phos phorus compensating implantation for PMOS transistor threshold voltage control avoids another resist step and photoresist process ing on gate oxide. The latter re8ult8 in an improved gate oxide integrity. The new implantation scheme has been sucessfully em ployed with the fabrication of a 1 Mbit SRAM on 150 mm wafers.