Profiling a warehouse-scale computer

Kanev, Svilen; Darago, Juan Pablo; Hazelwood, Kim; Ranganathan, Parthasarathy; Moseley, Tipp; Wei, Gu-Yeon; Brooks, David

doi:10.1145/2872887.2750392

Cited by 84 publications

(76 citation statements)

References 46 publications

(42 reference statements)

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“…II-B, benefits of large cache capacities disappear at high access latencies. Conventional DRAM caches are beneficial in alleviating the bandwidth bottleneck [29]; however, today's server CPUs are not bandwidth limited on scale-out workloads as shown in recent work [10] and corroborated by Google [39] and our own results. As such, conventional DRAM caches do not benefit these designs.…”

Section: Evaluation and Discussionsupporting

confidence: 83%

Farewell My Shared LLC! A Case for Private Die-Stacked DRAM Caches for Servers

Shahab

Zhu

Margaritov

et al. 2018

2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

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The slowdown in technology scaling mandates rethinking of conventional CPU architectures in a quest for higher performance and new capabilities. This work takes a step in this direction by questioning the value of on-chip shared lastlevel caches (LLCs) in server processors and argues for a better alternative. Shared LLCs have a number of limitations, including on-chip area constraints that limit storage capacity, long planar interconnect spans that increase access latency, and contention for the shared cache capacity that hurts performance under workload colocation. To overcome these limitations, we propose a Die-Stacked Private LLC Organization (SILO), which combines conventional on-chip private L1 (and optionally, L2) caches with a per-core private LLC in die-stacked DRAM. By stacking LLC slices directly above each core, SILO avoids long planar wire spans. The use of private caches inherently avoids inter-core cache contention. Last but not the least, engineering the DRAM for latency affords low access delays while still providing over 100MB of capacity per core in today's technology. Evaluation results show that SILO outperforms state-of-the-art conventional cache architectures on a range of scale-out and traditional workloads while delivering strong performance isolation under colocation.

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Section: Evaluation and Discussionsupporting

confidence: 83%

Farewell My Shared LLC! A Case for Private Die-Stacked DRAM Caches for Servers

Shahab

Zhu

Margaritov

et al. 2018

2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

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“…Increasing core counts, emergence of more data-intensive and latencycritical applications, and increasingly limited bandwidth in the memory system are together leading to higher memory latency. Thus, low-latency memory operation is now even more important to improving overall system performance [9,11,16,27,36,37,38,45,49,53,54,56,66,68,70,79].…”

Section: Introductionmentioning

confidence: 99%

Understanding Latency Variation in Modern DRAM Chips

Chang

Kashyap

Hassan

et al. 2016

Proceedings of the 2016 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Science

117

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Long DRAM latency is a critical performance bottleneck in current systems. DRAM access latency is defined by three fundamental operations that take place within the DRAM cell array: (i) activation of a memory row, which opens the row to perform accesses; (ii) precharge, which prepares the cell array for the next memory access; and (iii) restoration of the row, which restores the values of cells in the row that were destroyed due to activation. There is significant latency variation for each of these operations across the cells of a single DRAM chip due to irregularity in the manufacturing process. As a result, some cells are inherently faster to access, while others are inherently slower. Unfortunately, existing systems do not exploit this variation.The goal of this work is to (i) experimentally characterize and understand the latency variation across cells within a DRAM chip for these three fundamental DRAM operations, and (ii) develop new mechanisms that exploit our understanding of the latency variation to reliably improve performance. To this end, we comprehensively characterize 240 DRAM chips from three major vendors, and make several new observations about latency variation within DRAM. We find that (i) there is large latency variation across the cells for each of the three operations; (ii) variation characteristics exhibit significant spatial locality: slower cells are clustered in certain regions of a DRAM chip; and (iii) the three fundamental operations exhibit different reliability characteristics when the latency of each operation is reduced.Based on our observations, we propose Flexible-LatencY DRAM (FLY-DRAM), a mechanism that exploits latency variation across DRAM cells within a DRAM chip to improve system performance. The key idea of FLY-DRAM is to exploit the spatial locality of slower cells within DRAM, and access the faster DRAM regions with reduced latencies for the fundamental operations. Our evaluations show that FLY-DRAM improves the performance of a wide range of applications by 13.3%, 17.6%, and 19.5%, on average, for each of the three different vendors' real DRAM chips, in a simulated 8-core system. We conclude that the experimen-Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from permissions@acm.org. tal characterization and analysis of latency variation within modern DRAM, provided by this work, can lead to new techniques that improve DRAM and system performance.

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“…Figure 2.2 presents the cumulative distribution of cycles across workloads in Google data centers. The top 50 workloads account for only about 60% of the total WSC cycles, with a long tail accounting for the rest of the cycles [Kan+15].…”

Section: Workload Diversitymentioning

confidence: 99%