Program/Erase Scheme for Suppressing Interface Trap Generation in HfO₂-Based Ferroelectric Field Effect Transistor

Abstract

The endurance of the HfO2-based ferroelectric FET (FeFET) is investigated using various program/erase (PG/ER) pulse schemes. The ramp time (Tramp), which is the time to reach the PG/ER voltage, and the hold time (Thold), which is the time duration to maintain the PG/ER voltage, are adjusted, and thereafter, their influence on endurance is observed through the memory window, subthreshold slope, and threshold voltage of the FeFET while the FeFET is cycled up to 10 4 by a sequence of PG/ER pulses. Both parameters are closely related to depassivating interface traps, and it turns out that a long Tramp but short Thold are desirable to suppress the interface trap generation in FeFET. The relation between Tramp, Thold and the interface trap generation is explained by the transient built-in electric field (which is generated by the transiently trapped carrier in the gate oxide when the gate voltage is swept rapidly).

Smart pH Sensing: A Self-Sensitivity Programmable Platform with Multi-Functional Charge-Trap-Flash ISFET Technology

“…In the program mode, 50 pulses of 9.4 V with a duration of 100 ms were applied, normal state of the CTF-type MOSFET as the state without an external voltage, the state after applying a positive bias as the program state, and the state after applying a negative bias as the erasure state. The changes in the electrical characteristics were measured for each state [57][58][59].…”

Reliability of HfO2-Based Ferroelectric FETs: A Critical Review of Current and Future Challenges

“…So far, reliability investigations of HfO2-FeFETs focused on the evaluation of retention and endurance mostly. Recent studies however, pointed out the relevance of issues such as self-heating [87], hot-carrier injection [84], hot-atom damage [151], and radiation [85]. These effects need to be more thoroughly assessed to determine the feasibility of HfO2-FeFETs for new application scenarios such as in harsh environments (e.g., space).…”

Impact of the Crystal Structure of Interlayer on the Properties of Zr‐Doped Hafnia‐Based Ferroelectric Capacitor

“…With the emergence of complementary metal oxide semiconductorcompatible hafnium oxide-based ferroelectrics, ferroelectric memory devices are being considered as one of the candidates for next-generation memory applications because of their low cost, low power consumption, and excellent retention properties. [1][2][3][4][5][6] However, there exists some technical challenges to be addressed for ferroelectric memory to become mainstream in future memory market. One of them is to secure stable reliability characteristics, which is the most important for practical applications.…”