Program path analysis to bound cache-related preemption delay in preemptive real-time systems

Tomiyama,; Dutt, Nikil

doi:10.1109/hsc.2000.843709

Cited by 5 publications

(11 citation statements)

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“…Two analysis methods exists for such a purpose: the useful cache block (or UCB) [2], and the evicting cache block (or ECB) [3]. Further works in [4], [5] and [6] improve those methods and give a more precise CRPD upper-bound.…”

Section: A Cache Analysis Methodsmentioning

confidence: 99%

“…Even though there are many research projects about cache memory in real-time systems, such as the works in [2], [3], [4], [5] and [6], there is still a lack of practical implementation of those analysis methods in real-time scheduling analysis tools. In addition, a model based approach, which allows an abstraction of cache components, is necessary to combine the analysis tool with a system design and verification tool chain.…”

Section: Introductionmentioning

confidence: 99%

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Instruction Cache in Hard Real-Time Systems: Modeling and Integration in Scheduling Analysis Tools with AADL

Tran

Singhoff

Rubini

et al. 2014

2014 12th IEEE International Conference on Embedded and Ubiquitous Computing

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Cache prediction for real-time systems in a preemptive scheduling context is still an open issue despite its practical importance. In this paper, we propose a modeling approach for taking into account the cache memory in realtime scheduling analysis. The goal is to have a simple but practical implementation to handle the cache memory with a real-time scheduling analyzer. The proposed contribution consists of three main parts: (1) modeling the targeted system with the Architecture Analysis and Design Language (AADL), (2) applying the cache analysis methods in a real time scheduling analysis tool and (3) performing scheduling simulation to access schedulability. For such a purpose, we present an extension of both the scheduling analysis tool Cheddar and of the AADL modeling language in order to integrate the cache modeling and analysis methodology we proposed.Experiments are presented to illustrate our propositions. They provide results on analysis that show examples of the timing impact of task preemption as well as the increase in overall responses time of the task set. This impact is important and the developed tool provides means to precisely assess it.

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Section: A Cache Analysis Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Instruction Cache in Hard Real-Time Systems: Modeling and Integration in Scheduling Analysis Tools with AADL

Tran

Singhoff

Rubini

et al. 2014

2014 12th IEEE International Conference on Embedded and Ubiquitous Computing

View full text Add to dashboard Cite

show abstract

“…To analyse the effect of the preempting task, Tomiyama and Dutt introduced the concept of an evicting cache block [19]:…”

Section: Bounding the Crpdmentioning

confidence: 99%

“…Note that in case of nested preemption the set of ECBs in the formula is the union of all ECB sets of the preempting tasks [17,19].…”

Section: Bounding the Crpdmentioning

confidence: 99%

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Resilience analysis

Altmeyer

Maïza

Reineke

2010

Proceedings of the ACM SIGPLAN/SIGBED 2010 Conference on Languages, Compilers, and Tools for Embedded Systems

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In preemptive real-time systems, scheduling analyses need-in addition to the worst-case execution time-the context-switch cost. In case of preemption, the preempted and the preempting task may interfere on the cache memory. This interference leads to additional cache misses in the preempted task. The delay due to these cache misses is referred to as the cache-related preemption delay (CRPD), which constitutes the major part of the context-switch cost.In this paper, we present a new approach to compute tight bounds on the CRPD for LRU set-associative caches, based on analyses of both the preempted and the preempting task. Previous approaches analyzing both the preempted and the preempting task were either imprecise or unsound. As the basis of our approach we introduce the notion of resilience: The resilience of a memory block of the preempted task is the maximal number of memory accesses a preempting task could perform without causing an additional miss to this block. By computing lower bounds on the resilience of blocks and an upper bound on the number of accesses by a preempting task, one can guarantee that some blocks may not contribute to the CRPD. The CRPD analysis based on resilience considerably outperforms previous approaches.

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Accurate estimation of cache-related preemption delay

Negi¹,

Mitra²,

Roychoudhury³

First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721)

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Multitasked real-time systems often employ caches to boost performance. However the unpredictable dynamic behavior of caches makes schedulability analysis of such systems difficult. In particular, the effect of caches needs to be considered for estimating the inter-task interference. As the memory blocks of different tasks can map to the same cache blocks, preemption of a task may introduce additional cache misses. The time penalty introduced by these misses is called the Cache-Related Preemption Delay (CRPD).In this paper, we provide a program path analysis technique to estimate CRPD. Our technique performs path analysis of both the preempted and the preempting tasks. Furthermore, we improve the accuracy of the analysis by estimating the possible states of the entire cache at each possible preemption point rather than estimating the states of each cache block independently. To avoid incurring high space requirements, the cache states can be maintained symbolically as a Binary Decision Diagram. Experimental results indicate that we obtain tight CRPD estimates for realistic benchmarks.

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Program path analysis to bound cache-related preemption delay in preemptive real-time systems

Cited by 5 publications

References 0 publications

Instruction Cache in Hard Real-Time Systems: Modeling and Integration in Scheduling Analysis Tools with AADL

Instruction Cache in Hard Real-Time Systems: Modeling and Integration in Scheduling Analysis Tools with AADL

Resilience analysis

Accurate estimation of cache-related preemption delay

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