Program slicing for ATPG-based property checking

Vedula, V.M.; Townsend, Whitney J.; Abraham, Jacob A.

doi:10.1109/icvd.2004.1260983

Cited by 13 publications

(6 citation statements)

References 27 publications

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“…The systematic approach, with a strong theoretical basis for using program slicing on HDL programs, has also been successfully applied to accelerate a bounded model checking approach based on sequential ATPG techniques [16].…”

Section: Program Slicing Methodologymentioning

confidence: 99%

See 1 more Smart Citation

Taming the Complexity of STE-based Design Verification Using Program Slicing

Vedula

Andersen

Abraham

2006

2006 IEEE International High Level Design Validation and Test Workshop

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This paper presents the development of a hierarchical methodology for speeding-up a Symbolic Trajectory Evaluation (STE) based verification flow, using "program slicing" techniques. An overview of the proposed methodology is described, along with the details of a prototype tool that has been developed to automate the approach. The tool, called FACTOR, has been successfully applied to reduce the size ofthe RTL implementation ofafloating -point unit in a Intel® Pentium® 4 processor model neededforformally verifying an embedded module. The existing proof specification for the module was validated using Forte, Intel's STE tool, on both the original and the reduced model. A comparison of the results demonstrates the effectiveness of the methodology, and its immense potential to scale up the verificationflow to larger design sizes.

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Section: Program Slicing Methodologymentioning

confidence: 99%

“…The program slicing methodology [5] [16] for HDL models has been tailored to suit Intel's verification flow, as described in this sub-section. A digital design that is implemented in an HDL is often a hierarchical composition of several modules.…”

Section: Verification Methodologymentioning

confidence: 99%

Taming the Complexity of STE-based Design Verification Using Program Slicing

Vedula

Andersen

Abraham

2006

2006 IEEE International High Level Design Validation and Test Workshop

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“…On the other hand, in sequential programs, functions are called explicitly when the program controls reaches a procedure call. To address these issues, much research into program slicing techniques for HDL designs has been conducted [9,4,11,22,23,24].…”

Section: Previous Workmentioning

confidence: 99%

Reducing verification overhead with RTL slicing

Ou¹,

Saab²,

Qiang

et al. 2007

Proceedings of the 17th ACM Great Lakes Symposium on VLSI

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Design complexity is increasing with every technology generation, causing verification tools to require large amounts of resources. In this paper, we develop a technique to reduce the complexity of verifying digital designs described in a Hardware Description Language (HDL). For a given property to be verified, we derive an HDL executable design slice that is behaviorally equivalent to the original design. The slice is less complex than the original design and requires fewer resources for analysis by a verification tool. The slicer is implemented as a pre-processor to SMV, a SAT-based verification tool, and Formal, an ATPG-based verification tool. Experimental results on the USB2.0 IP core show that RTL slicing reduces both CPU and memory overhead for both SMV and Formal. This reduction allows the verification tools to effectively deal with complex designs.

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“…However, these methods have been in use for the purpose of localizing errors in software development, assuming the underlying hardware works well. Similar techniques have been proposed to assist in the hardware development process [20], [21]. These, however, refer to slicing of the RTL code while we propose to conduct dynamic slicing of the test-case.…”

Section: Related Workmentioning

confidence: 99%

Effective post-silicon failure localization using dynamic program slicing

Friedler¹,

Kadry²,

Morgenshtein³

et al. 2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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Abstract-In post-silicon functional validation, one of the most complex and time-consuming processes is the localization of an instruction that exposes a bug detected at system level. The task is particularly difficult due to the silicon's limited observability and the long time between a failure's occurrence and its detection.We propose a novel method that automates the architectural localization of post-silicon test-case failures. Our proposed tool analyzes a failing test-case, while leveraging the information derived from executing the test on an Instruction Set software Simulator (ISS), to identify a set of instructions that could lead to the faulty final state. The proposed failure localization process comprises the creation of a resource dependency graph based on the execution of the test-case on the ISS, determining a program slice of instructions that influence the faulty resources, and the reduction of the set of suspicious instructions by leveraging the knowledge of the correct resources.We evaluate our proposed solution through extensive experiments. Experimental results show that, in over 97% of all cases, our method was able to narrow down the list of suspicious instructions to under 2 instructions, on average, out of over 200. In over 59% of all cases, our method correctly reduced a test-case to a single faulty instruction.

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Program slicing for ATPG-based property checking

Cited by 13 publications

References 27 publications

Taming the Complexity of STE-based Design Verification Using Program Slicing

Taming the Complexity of STE-based Design Verification Using Program Slicing

Reducing verification overhead with RTL slicing

Effective post-silicon failure localization using dynamic program slicing

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