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This paper presents a concurrent error correcting adder design employing fault masking through a combination of time and hardware redundancy. This new method, Quadruple Time Redundancy, is compared with a non-redundant adder, a Triple Modular Redundancy adder, and a Time Shared Triple Modular Redundancy adder with respect to the hardware complexity and the delay for adders of various sizes. In comparison with Time Shared Triple Modular Redundancy to which it is most closely related, Quadruple Time Redundancy results in a 40% -55% reduction in hardware complexity while incurring a reasonable delay zncrease.

This paper presents a novel technique for abstracting designs in order to increase the efficiency of formal property checking. Bounded Model Checking (BMC), using Satisfiability (SAT) techniques, are beginning to be widely used for checking properties of designs. Recent approaches using sequential ATPG techniques, which harness the structural information of the design, have been shown to perform better than SAT-based BMC. However, these techniques require an effective methodology to deal with the size of commercial designs. A program slicing methodology that has been shown to accelerate sequential ATPG is adapted and integrated into an ATPG-based BMC framework. Furthermore, a generalization of the ATPG-based approach, which checks for unbounded liveness, is also presented.

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