A comparison of Dadda and Wallace multiplier delays

Townsend, Whitney J.; Swartzlander, Earl E.; Abraham, Jacob A.

doi:10.1117/12.507012

Cited by 89 publications

(24 citation statements)

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“…Wallace tree is an efficient hardware implementation of a digital circuit that multiplies two integers [7]. Using this method, a three step process is used to multiply two integer numbers.…”

Section: Wallace Tree Multipliermentioning

confidence: 99%

ASIC realization and performance evaluation of scalable microprogrammed FIR filters using Wallace tree and Vedic multipliers

Aljuffri

Alnahdi

Hemaid

et al. 2015

2015 IEEE 15th International Conference on Environment and Electrical Engineering (EEEIC)

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Finite impulse response (FIR) filter is widely used in digital signal processing (DSP) and communication systems. Multiplication is an essential and complex building block used in the realization of FIR filters. In this paper, Wallace tree and Vedic multipliers are used for efficient realization of sequential and parallel scalable microprogrammed FIR filter architectures. The designs are coded in Verilog hardware description language and realized using LFoundry 150nm standard-cell based technology. ASIC realization results are presented and analyzed in order to evaluate the performance of both FIR filters.

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Section: Wallace Tree Multipliermentioning

confidence: 99%

ASIC realization and performance evaluation of scalable microprogrammed FIR filters using Wallace tree and Vedic multipliers

Aljuffri

Alnahdi

Hemaid

et al. 2015

2015 IEEE 15th International Conference on Environment and Electrical Engineering (EEEIC)

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“…A method for fast multiplication was originally proposed by Wallace [9]. Wallace tree is an efficient hardware implementation of a digital circuit that multiplies two integers.…”

Section: Wallace Tree Multiplier Designmentioning

confidence: 99%

FPGA implementation of scalable microprogrammed FIR filter architectures using Wallace tree and Vedic multipliers

Aljuffri

Badawi

BenSaleh

et al. 2015

2015 Third International Conference on Technological Advances in Electrical, Electronics and Computer Engineering (TAEECE)

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Field programmable gate array (FPGA) is widely used for efficient hardware realization of digital signal processing (DSP) circuits and systems. Finite impulse response (FIR) filter is the core of any DSP and communication systems. To improve the performance of FIR filter, an efficient multiplier is required. Wallace tree and Vedic multipliers are used in this paper for the implementation of sequential and parallel microprogrammed FIR filter architectures. The designs are realized using Xilinx Virtex-5 FPGA. FPGA implementation results are presented and analyzed. Based on the implementation results, sequential FIR filter using Wallace tree multiplier/carry skip adder combination proves to be more efficient as compared to other multiplier/adder combinations.

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“…The production of carry is the major speed limitation in any adder. Generally Carry Save Adder can be used for adding more than three n-bit binary numbers [8].…”

Section: Introductionmentioning

confidence: 99%

Design of area efficient and low power multipliers using multiplexer based full adder

Murugeswari

Mohideen

2014

Second International Conference on Current Trends in Engineering and Technology - ICCTET 2014

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This paper presents the modification of existing prominent multipliers like Wallace multiplier and Truncated Multiplier in order to improvise them in terms of power and area. In the existing Wallace multiplier architecture, the Carry Save Adder is replaced with Modified Carry Save Adder (MCSA)and further the full adder in the MCSA is implemented using Multiplexer. Similarly the regular full adder in the Truncated multiplier has been replaced with mux based full adder to achieve low area and power. Simulation of 8 x 8 Multiplier has been carried out with Modelsim 6.3c and Synthesis is carried out by Xilinx10.1. Results obtained show that the proposed modified multipliers offer low power and reduced area than the existing Multipliers.

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A comparison of Dadda and Wallace multiplier delays

Cited by 89 publications

References 0 publications

ASIC realization and performance evaluation of scalable microprogrammed FIR filters using Wallace tree and Vedic multipliers

ASIC realization and performance evaluation of scalable microprogrammed FIR filters using Wallace tree and Vedic multipliers

FPGA implementation of scalable microprogrammed FIR filter architectures using Wallace tree and Vedic multipliers

Design of area efficient and low power multipliers using multiplexer based full adder

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