In this letter, a novel scalable and modular design of direct form sequential finite impulse response (FIR) filter using microprogrammed control unit is proposed that can be efficiently realized in field programmable gate array (FPGA) or application specific integrated circuit (ASIC). The proposed design is suitable for sensor processing subsystem used in wireless sensor network (WSN) nodes. This is demonstrated by evaluating a sample 4-tap FIR filter on various FPGA platforms and ASIC technologies. The evaluation result shows good area/power efficiency and flexibility by using microprogrammed architecture for such applications.

Multi-Processor System-on-Chips (MPSoCs) are popular computational platforms for a wide variety of applications due to their energy efficiency and flexibility. Like many other platforms they are vulnerable to Side Channel Attacks (SCAs). In particular, Logical SCAs (LSCAs) are very powerful as sensitive information can be retrieved by simply observing system properties that depend on the victim's software execution on the MPSoC. Unfortunately, many of the current protection mechanisms are either platform dependent or are effective only against a reduced set of attacks. In this work, we present Guard-NoC, a secure Network-on-Chip (NoC) architecture able to protect MPSoCs against a wide variety of LSCAs. The secure NoC employs three application-independent strategies to hide and isolate sensitive information: i) blinding the execution time of operations; ii) masking the execution time of operations; and iii) dual communication strategy (i.e., use packet and circuit switching simultaneously). Our results show that our secure NoC is resilient against practical LSCAs and leaks almost no information while having a minimal area and power overhead.

Side-channel attacks (SCAs) are powerful attacks that could be used to retrieve keys from electronic devices. Several physical leakage sources can be exploited in SCAs, such as power, time, heat, and so on. Heat is one of the side-channels that is not frequently analyzed by attackers in the literature due to the high noise associated with thermal traces. This article investigates the practicality of adapting power-based SCAs [i.e., correlation power analysis (CPA) and deep-learning-based power attacks (DL-based PA)] for thermal attacks and refer to them as correlation thermal attack (CTA) and DL-based thermal attack (DL-based TA). In addition, we introduce a new attack called progressive CTA (PCTA). We evaluate the different thermal SCAs against an unprotected and protected software implementation of Rivest-Shamir-Adleman (RSA). Our results show the practicality of the three attacks (i.e. CTA, DL-based TA, and PCTA) as a 100% key recovery is realized.

Field programmable gate array (FPGA) is widely used for efficient hardware realization of digital signal processing (DSP) circuits and systems. Finite impulse response (FIR) filter is the core of any DSP and communication systems. To improve the performance of FIR filter, an efficient multiplier is required. Wallace tree and Vedic multipliers are used in this paper for the implementation of sequential and parallel microprogrammed FIR filter architectures. The designs are realized using Xilinx Virtex-5 FPGA. FPGA implementation results are presented and analyzed. Based on the implementation results, sequential FIR filter using Wallace tree multiplier/carry skip adder combination proves to be more efficient as compared to other multiplier/adder combinations.