FPGA implementation of scalable microprogrammed FIR filter architectures using Wallace tree and Vedic multipliers

Aljuffri, Abdullah; Badawi, Aiman; BenSaleh, Mohammed S.; Obeid, Abdulfattah M.; Qasim, Syed Manzoor

doi:10.1109/taeece.2015.7113619

Cited by 13 publications

(4 citation statements)

References 11 publications

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“…It also uses the same linear projection d 4 that was used in design option #3. The corresponding projection matrix is given by (29). The PE index associated with a point p in the DG is given by (30).…”

Section: Design Option #6: Using S 2 = [1 1] and D 4 = [0 1] Tmentioning

confidence: 99%

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Decimator systolic arrays design space exploration for multirate signal processing applications

Shoukry

Gebali

Agathoklis

2019

IET Circuits, Devices & Systems

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This study presents a new systolic array structure for a decimator that merges the antialiasing finite impulse response (FIR) filter with the downsampler. The development of the structure is based on a systematic methodology. Using this methodology, a dependence graph for the decimator was obtained that combined the antialiasing filter and the downsampler. Different data scheduling and projection operations were developed to obtain different proposed designs. Six systolic array design options were obtained and evaluated. The fastest design was selected for hardware implementation and compared with the other two well known decimator designs; namely, conventional design, in which the antialiasing filter is followed by a downsampling and the polyphase design, in which a commutator is followed by the polyphase antialiasing filter. Fieldprogrammable gate array implementations for the proposed and the other two designs confirm that the proposed decimator implementation outperforms in terms of area, speed, and power as the decimation factor increases regardless of the number of FIR filter coefficients.

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Section: Design Option #6: Using S 2 = [1 1] and D 4 = [0 1] Tmentioning

confidence: 99%

“…Aljuffri , et al [29] used Wallace tree and Vedic multipliers for implementation of 8‐tap and 16‐tap sequential and parallel micro‐programmed FIR filters architectures. The designs are realised using FPGA.…”

Section: Introduction and Related Workmentioning

confidence: 99%

Decimator systolic arrays design space exploration for multirate signal processing applications

Shoukry

Gebali

Agathoklis

2019

IET Circuits, Devices & Systems

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“…I this work Different multiplier and adder combinations were employed in this to construct microprogrammed sequential and parallel FIR filter topologies on Xilinx Virtex-5 FPGA. Utilising the Synplify Pro programme to analyse the performance of different architectures, it was discovered that the sequential FIR filter with Wallace tree multiplier/Carry skip adder combination performed more efficiently than the other combinations tested [5]. This study of work states that When a FIR filter is combined with a Booth multiplier and carry select adder, it performs better than previous systems in terms of delay, area, and power consumption.…”

Section: Introductionmentioning

confidence: 99%

Comparative Analysis of FIR Filter Design using Different Multipliers and CLA adder

2023

IRJMETS

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A comparative analysis study of FIR filter implementation reveals that employing various multiplier design strategies can help identify a high-quality response filter from a range of FIR filters. The significance of filters stems from the rapid growth of communication systems in recent times, as they play a crucial role in these systems. Filters are extensively utilized in digital signal processing applications to achieve objectives such as noise reduction, signal amplification, and data compression. Their primary purpose is to enable the recovery of the original signal at the receiver side, allowing for effective communication. Even if the filtered output is relatively small, a strong filtered signal can be sent to an amplifier to restore the original signal. To achieve this, it is essential for the filter to be both efficient and well-designed. Given the increasing number of communication systems, selecting the right filter becomes paramount to ensure optimal performance and maintain the integrity of the transmitted signal. By comparing the implementation stats of various FIR filters and considering different multiplier design strategies, it is possible to identify a high-quality response filter. Such a filter will contribute to the effective functioning of communication systems by enabling noise reduction, signal amplification, and data compression, ultimately leading to successful signal recovery at the receiver end.

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“…Multipliers and adders play a dominant role in the optimal realisation of FIR filters [4,5]. The objective of this chapter is to further explore this technique using Wallace tree multiplier with different adder configurations for optimal realisation of FIR filter [6]. The proposed design is modular and scalable which enables realisation of higher-order FIR filter.…”

Section: Introductionmentioning

confidence: 99%

Towards Optimised FPGA Realisation of Microprogrammed Control Unit Based FIR Filters

Qasim¹,

BenSaleh²,

Obeid³

2019

Control Theory in Engineering [Working Title]

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Finite impulse response (FIR) filter is one of the most common type of digital filter used in digital signal processing (DSP) applications. An FIR filter is usually realised in hardware using multipliers, adders and registers. Field programmable gate arrays (FPGAs) have been widely explored for the hardware realisation of FIR filters using different algorithms and techniques. One such technique that has recently gained considerable attention is the use of microprogrammed control unit (MPCU) in designing FIR filters. In this chapter, we further explore MPCU technique for optimised hardware realisation of digital FIR filter. To evaluate the performance, two different architectures of FIR filter are designed using Wallace tree multiplier. Both the architectures are coded in Verilog hardware description language (HDL). The performance is analysed by evaluating the resource utilisation and timing reports of Virtex-5 FPGA generated by the Synopsys Synplify Pro tool. Based on the implementation results, as compared to conventional design, Wallace tree multiplier using carry skip adder (CSKA) provides optimal digital FIR filter.

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FPGA implementation of scalable microprogrammed FIR filter architectures using Wallace tree and Vedic multipliers

Cited by 13 publications

References 11 publications

Decimator systolic arrays design space exploration for multirate signal processing applications

Decimator systolic arrays design space exploration for multirate signal processing applications

Comparative Analysis of FIR Filter Design using Different Multipliers and CLA adder

Towards Optimised FPGA Realisation of Microprogrammed Control Unit Based FIR Filters

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