Program Slicing of Hardware Description Languages

Clarke, Edmund M.; Fujita, Masahiro; Sunitha, R; Reps, Thomas; Shankar, Subash; Teitelbaum, Tim

doi:10.1007/3-540-48153-2_22

Cited by 54 publications

(12 citation statements)

References 26 publications

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“…The sliced program is smaller than the original program and is functionally equivalent with respect to the slicing criterion. In this paper, we focus on works that use slicing as a program reduction tool for model checking as shown in Clarke et al (1999), Hatcliff et al (1999), and Millett and Teitelbaum (1998).…”

Section: Static Analysismentioning

confidence: 99%

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Model checking programs

Visser

Havelund

Brat

et al. 2000

Proceedings ASE 2000. Fifteenth IEEE International Conference on Automated Software Engineering

596

741

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Abstract. The majority of work carried out in the formal methods community throughout the last three decades has (for good reasons) been devoted to special languages designed to make it easier to experiment with mechanized formal methods such as theorem provers, proof checkers and model checkers. In this paper we will attempt to give convincing arguments for why we believe it is time for the formal methods community to shift some of its attention towards the analysis of programs written in modern programming languages. In keeping with this philosophy we have developed a verification and testing environment for Java, called Java PathFinder (JPF), which integrates model checking, program analysis and testing. Part of this work has consisted of building a new Java Virtual Machine that interprets Java bytecode. JPF uses state compression to handle big states, and partial order and symmetry reduction, slicing, abstraction, and runtime analysis techniques to reduce the state space. JPF has been applied to a real-time avionics operating system developed at Honeywell, illustrating an intricate error, and to a model of a spacecraft controller, illustrating the combination of abstraction, runtime analysis, and slicing with model checking.

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Section: Static Analysismentioning

confidence: 99%

“…A similar approach has been applied to slicing and model checking VHDL programs (Clarke et al, 1999). Since VHDL programs consist of concurrent processes the authors had to adapt traditional slicing techniques to handle concurrency.…”

Section: Static Analysismentioning

confidence: 99%

Model checking programs

Visser

Havelund

Brat

et al. 2000

Proceedings ASE 2000. Fifteenth IEEE International Conference on Automated Software Engineering

596

741

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“…They used the VHDL simulation semantic to explain the slice model based on a new dependence graph called signal dependence to emulate the concurrent execution of HDL, which is an inter-process dependence. Clarke et al (1999) proposed an automated slicing technique for VHDL. They introduced System Dependence Graphs (SDG) and presented a mapping from VHDL to generic graph-reachability representation.…”

Section: Related Work and Backgroundsmentioning

confidence: 99%

Conditioned Slicing for Efficient Multiway Decision Graphs Model-Checker

Elmansori¹

2013

Journal of Computer Science

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Integrating formal verification techniques into the hardware design process provides the means to rigorously prove critical properties. However, most automatic verification techniques, such as model checking, are only effectively applicable to designs of limited sizes due to the state explosion problem. The Multiway Decision Graphs (MDG) method is an efficient method to define hardware designs into more abstract environments; however, the MDG model checker (MDG-MC) still suffers from the state explosion problem. Furthermore, all the backward reduction algorithms cannot be used in MDG, due to the presence of abstract state variables. In this study, an efficient extractor for MDG Hardware Descrpiton Languge (MDG-HDL) is introduced based on static (SS-MDG) and conditioned (CS-MDG) program slicing techniques. The techniques can obtain a chaining slice for given signals of interest. The main advantages of these techniques are: It has no MDG-HDL coding style limitation, it is accurate and it is competent in dealing with various MDG-HDL constructions. The main motivation for introducing this approach is to tackle the state explosion problem of MDG-MC that big MDG-HDL may cause. We apply our proposed techniques on different MDG-HDL designs and our analyses have shown that the proposed reduction techniques resulted in significantly improved performance of the MDG-MC. In this study, we present a general idea of program slicing, a discussion of how to slice MDG-HDL programs, implementation of the tool and a brief overview of some applications and experimental results. The underlying method and the tool based on it need to be empirically evaluated when applying to various applications.

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“…Program slicing has been well studied in the context of software engineering [11], programming languages [18], and more recently, in the context of slicing hardware description languages [10], [20]. We define a new notion of program slicing for microprocessor descriptions, viz., slicing based on the instruction which is being executed.…”

Section: Instruction-driven Slicingmentioning

confidence: 99%