Program Slicing of Hardware Description Languages

Clarke, Edmund M.; Fujita, M.; Sunitha, R; Reps, Thomas; Shankar, Subash

doi:10.21236/ada363556

Cited by 19 publications

(20 citation statements)

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“…Using this notion, Iwaihara et al [14] suggested an approach to use program slicing for analyzing VHDL designs, and presented the reduction obtained on a set of benchmarks using each of the outputs as the slicing criterion. An automated program slicing approach for VHDL was proposed by Clarke et al [15], in which VHDL constructs were mapped onto constructs for C-like procedural languages. The primary focus of their work was to reduce the reachable state-space for formal property verification.…”

Section: Program Slicing Methodologymentioning

confidence: 99%

“…The primary focus of their work was to reduce the reachable state-space for formal property verification. Although these two contributions [14] [15] suggested potential applications to simulation, functional testing, regression testing, testability analysis, design modification and maintenance, they did not provide any concrete supporting experimental results.…”

Section: Program Slicing Methodologymentioning

confidence: 99%

See 1 more Smart Citation

Taming the Complexity of STE-based Design Verification Using Program Slicing

Vedula

Andersen

Abraham

2006

2006 IEEE International High Level Design Validation and Test Workshop

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This paper presents the development of a hierarchical methodology for speeding-up a Symbolic Trajectory Evaluation (STE) based verification flow, using "program slicing" techniques. An overview of the proposed methodology is described, along with the details of a prototype tool that has been developed to automate the approach. The tool, called FACTOR, has been successfully applied to reduce the size ofthe RTL implementation ofafloating -point unit in a Intel® Pentium® 4 processor model neededforformally verifying an embedded module. The existing proof specification for the module was validated using Forte, Intel's STE tool, on both the original and the reduced model. A comparison of the results demonstrates the effectiveness of the methodology, and its immense potential to scale up the verificationflow to larger design sizes.

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Section: Program Slicing Methodologymentioning

confidence: 99%

Section: Program Slicing Methodologymentioning

confidence: 99%

Taming the Complexity of STE-based Design Verification Using Program Slicing

Vedula

Andersen

Abraham

2006

2006 IEEE International High Level Design Validation and Test Workshop

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“…This causes state space explosion, which makes exploration infeasible by the model checker in the reasonable time and memory usage. To overcome this issue, basic MC algorithms have been enhanced in various ways, some of which are symmetry reduction, partial order reduction [35,40,41], abstraction [42], static [43][44][45] and dynamic analysis [46].…”

Section: Model Checkingmentioning

confidence: 99%

“…For example, in JPF (used as the underlying model checker in this study), applying the space reduction techniques has led to reduce the state space of the programs and the taken time for checking them. JPF is equipped with the techniques such as partial order and symmetry reduction [39][40][41], abstraction [42], static analysis [43,45,46], and dynamic analysis [58] which reduce the state space. During the JPF run, each created state is compared with previously visited states and is not expanded if it matches to any of them.…”

Section: Model Checkingmentioning

confidence: 99%

Automated program repair using genetic programming and model checking

2016

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Automated program repair is still a highly challenging problem mainly due to the reliance of the current techniques on test cases to validate candidate patches. This leads to the increasing unreliability of the final patches since test cases are partial specifications of the software. In the present paper, an automated program repair method is proposed by integrating genetic programming (GP) and model checking (MC). Due to its capabilities to verify the finite state systems, MC is employed as an appropriate criterion for evolving programs to calculate the fitness in GP. The application of MC for the fitness evaluation, which is novel in the context of program repair, addresses an important gap in the current heuristic approaches to the program repair. Being focused on fault detection based on the desired aspects, it enables the programmers to detect faults according to the definition of properties. Creating a general method, this characteristic can be effectively customized for different domains of application and the corresponding faults. Apart from various types of faults, the proposed method is capable of handling concurrency bugs which are not the case in many general repair methods. To evaluate the proposed method, it was implemented as a tool, named JBF, to repair Java programs. To meet the objectives of the study, some experiments were conducted in which certain programs with known bugs were automatically repaired by the JBF tool. The obtained results are encouraging and remarkably promising.

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“…To improve the efficiency of formal verification process, Clarke [3] proposed a VHDL slicing method in which a VHDL design is transformed into sequential program constructs and a sequential program slicing tool is applied on the transformed VHDL code. In this technique, the user is required to specify statements and location of signals in in the slicing criterion.…”

Section: Introductionmentioning

confidence: 99%

HDL Program Slicing to Reduce Bounded Model Checking Search Overhead

Saab

Abraham

2006

2006 IEEE International Test Conference

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The size of the Hardware Description Model for a complex modern digital system is increasing rapidly. CAD tools used to analyze these models are challenged by this increase in model complexity. In this paper, we present a technique that extracts for a given set of variables, a smaller HDL executable design slice that includes all the behavioral elements that affect those variables directly or indirectly. The design slice when compiled produces a behavior for the set of variables equivalent to the one computed by the original unsliced design. ATPG and verification tools analyzing this design could use the sliced model to reduce computation overhead. We implemented this technique in a computer program and evaluated its impact on the bounded model checker, SMV. Our results show a reduction for both CPU time and memory needed by SMV to verify a publicly available model of the USB 2.0 IP core.

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Program Slicing of Hardware Description Languages

Cited by 19 publications

References 0 publications

Taming the Complexity of STE-based Design Verification Using Program Slicing

Taming the Complexity of STE-based Design Verification Using Program Slicing

Automated program repair using genetic programming and model checking

HDL Program Slicing to Reduce Bounded Model Checking Search Overhead

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