Programmable Logic Devices (PLDs) in Practical Applications

Matsumoto, Tsutomu; Yamaguchi, Yoshiki; Osana, Yasunori

doi:10.1007/978-981-13-0824-6_7

Cited by 3 publications

(3 citation statements)

References 38 publications

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“…In a CLB of Virtex-7 [36], it is possible to form either two 7-LUTs or a single 8-LUT using dedicated multiplexors. However, the total number of inputs and state variables of an FSM can significantly exceed 8 [17]. This leads to an imbalance between the characteristics of LUTs and SBFs (2) and (3).…”

Section: Related Workmentioning

confidence: 99%

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Using Codes of Output Collections for Hardware Reduction in Circuits of LUT-Based Finite State Machines

et al. 2022

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A method is proposed which aims to reduce the hardware in FPGA-based circuits of Mealy finite state machines (FSMs). The proposed method is a type of structural decomposition method. Its main goal is the reducing the number of look-up table (LUT) elements in FSM circuits compared to the three-block FSM circuit. The main idea of the proposed method is the using codes of collections of FSM outputs for replacing the FSM inputs and state variables. The interstate transitions are defined using collections of outputs generated in two adjacent cycles of synchronization. One, of output collection codes, is kept into a register. To optimize block-generating FSM outputs, a new type of state codes is proposed. A state is encoded as an element of some class of states. This approach allows both the number of logic levels and inter-level interconnections in LUT-based FSM circuit to be diminished. An example of an LUT-based Mealy FSM circuit with the proposed method applied is shown. Moreover, the results of our research are represented. The research was conducted using the CAD tool Vivado by Xilinx. The experiments prove that the proposed approach allows the reduction of hardware compared with such known methods as Auto and One-hot of Vivado, and JEDI. Moreover, the proposed approach gives better results than a method based on the simultaneous replacement of inputs and encoding collections of outputs. Compared to circuits of the three-block FSMs, the LUT counts are reduced by an average of 10.07% without significant reduction in the value of operating frequency. The gain in LUT counts increases with the increasing the numbers of FSM states and inputs.

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Section: Related Workmentioning

confidence: 99%

“…Today, a lot of digital systems are implemented using field programmable gate arrays (FPGAs) [17]. For example, FPGAs are widely used for implementing hardware accelerators [18].…”

Section: Introductionmentioning

confidence: 99%

Using Codes of Output Collections for Hardware Reduction in Circuits of LUT-Based Finite State Machines

et al. 2022

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“…The main advantage of PLDs is their capability to be re-configured [1]. This allows companies to change the product logic without modifying the printed-circuit board (PCB) in which it is used, as long as the PLD of choice is available.…”

Section: Introductionmentioning

confidence: 99%

Dealing with the Obsolescence of Programmable Logic Devices (PLDs) in Electronic Products

Fabbro¹,

Madureira²,

Herve³

et al. 2021

Anais Do XLVIII Seminário Integrado De Software E Hardware (SEMISH 2021)

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PLDs are commonplace in today's electronic products. When such devices reach their end-of-life, the product manufacturer must find a viable solution, both technical and economical. Replacing a PLD by an ASIC is a viable alternative that is explored in this paper, using a real case as an example. Boundary business conditions for deciding for this option are presented. Depending on these conditions, obsolescence can be seen as an opportunity for the improvement of the product, taking advantage of other benefits that an ASIC brings. As an ASIC development can be seen as risky, pricy, and as having a long time to market, a structured ASIC platform, called ICX, that mitigates all of these three aspects, is also presented.

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