Programming model for a heterogeneous x86 platform

Abstract

The client computing platform is moving towards a heterogeneous architecture consisting of a combination of cores focused on scalar performance, and a set of throughput-oriented cores. The throughput oriented cores (e.g. a GPU) may be connected over both coherent and non-coherent interconnects, and have different ISAs. This paper describes a programming model for such heterogeneous platforms. We discuss the language constructs, runtime implementation, and the memory model for such a programming environment. We implemented this programming environment in a x86 heterogeneous platform simulator. We ported a number of workloads to our programming environment, and present the performance of our programming environment on these workloads.

Exploring Traditional and Emerging Parallel Programming Models Using a Proxy Application

“…Chamberlain [17] and Saha [23] present multiple models as a theoretical foundation to point out the benefits of the authors' own approach. However, no study exists in which a single, realistic application is used to compare a wide range of traditional and emerging programming models or approaches in a systematic way, covering a wide range of aspects, including expressiveness, performance, productivity and manageability.…”

Harmony: Collection and analysis of parallel block vectors

“…Recent interest in heterogeneous multicore architectures spans not only the architecture community but operating systems, high-performance computing, programming languages, and others [14,37,18,23,2,8,27]. The principle idea behind heterogeneous processing is specialization: different cores on a heterogeneous machine can address the varied compute needs of modern workloads while maximizing hardware performance and efficiency.…”

Fast and efficient automatic memory management for GPUs using compiler-assisted runtime coherence scheme

“…Saha et al describe a programming model for C on heterogeneous x86 platforms [17] which provides a logical shared address space between the CPU and an accelerator modeled on the Larrabee [18]. Coherence is maintained by the CPU and the accelerator by intercepting reads and writes using the operating system's memory protection mechanisms.…”

“…• Designed as a compiler-runtime hybrid scheme, it requires no OS or hardware support (unlike [6,9,17]), and is therefore widely applicable to accelerators beyond GPUs.…”