Programming Strategies for Irregular Algorithms on the Emu Chick

Abstract

The Emu Chick prototype implements migratory memory-side processing in a novel hardware system. Rather than transferring large amounts of data across the system interconnect, the Emu Chick moves lightweight thread contexts to near-memory cores before the beginning of each remote memory read. Previous work has characterized the performance of the Chick prototype in terms of memory bandwidth and programming differences from more typical, non-migratory platforms, but there has not yet been an analysis of algorithms on this system. This work evaluates irregular algorithms that could benefit from the lightweight, memory-side processing of the Chick and demonstrates techniques and optimization strategies for achieving performance in sparse matrix-vector multiply operation (SpMV), breadth-first search (BFS), and graph alignment across up to eight distributed nodes encompassing 64 nodelets in the Chick system. We also define and justify relative metrics to compare prototype FPGA-based hardware with established ASIC architectures. The Chick currently supports up to 68x scaling for graph alignment, 80 MTEPS for BFS on balanced graphs, and 50% of measured STREAM bandwidth for SpMV.

Wrangling Rogues: Managing Experimental Post-Moore Architectures

“…Although there are multiple vectors for growth and improved infrastructure with the Rogues Gallery, the testbed has already led to some early successes. These positive outcomes include several published academic papers [10,11,14,29,35], support for PhD thesis research, ongoing collaborations with external academic, industry, and government users, and a job offer from one of the rogue startups for at least one of our PhD students at Georgia Tech. We look forward to new infrastructure developments, student-focused activities like the Rogues Gallery VIP class, and further collaborations with other post-Moore architecture and system evaluation labs to help drive the next phase of the Rogues Gallery's evolution.…”

Performance Impact of Memory Channels on Sparse and Irregular Algorithms

“…Similarly, the Emu Chick architecture [9] divides a DRAM channel into multiple "Narrow-Channel DIMMs" (NCDIMMs) which allow for more fine-grained access for irregular applications. Recent tests of BFS and small-scale graph analytics applications [11] shows promise for the NCDIMM approach with stable performance for different real-world sparse matrix multiply inputs and comparable performance with x86 platforms for BFS on balanced (Erdös-Rényi) graphs. However, performance of graph analytics on the Emu Chick is currently limited not by the memory subsystem but by data layout and workload imbalance issues that create thread migration hotspots across the Chick's distributed nodes.…”