Programming the Adapteva Epiphany 64-Core Network-on-Chip Coprocessor

Abstract-Recent years have seen a growing trend towards the introduction of more advanced manycore processors. On the other hand, there is also a growing popularity for cheap, creditcard-sized, devices offering more and more advanced features and computational power.In this paper we evaluate Parallella -a small board with the Epiphany manycore coprocessor consisting of sixteen MIMD cores connected by a mesh network-on-a-chip. Our tests are based on classical genetic algorithms. We discuss some possible optimizations and issues that arise from the architecture of the board. Although we achieve significant speed improvements, there are issues, such us the limited local memory size and slow memory access, that make the implementation of efficient code for Parallella difficult.

show abstract

“…These speeds and significant differences to the theoretical values are similar to other results [17].…”

Section: A Microbenchmarks 1) Memory Bandwidthsupporting

confidence: 91%

Efficient parallel execution of genetic algorithms on Epiphany manycore processor

Faber

Boryczko

2016

Annals of Computer Science and Information Systems

View full text Add to dashboard Cite

show abstract

“…Similarly, Kalray MPPA-256 features a communication library that shares some similarity with POSIX [25] and a specific interface for one-sided communications [18]. Finally, a particular communication API is provided to developers that target the Adapteva Epiphany architecture [28]. On the other hand, there exist solutions based on well-known distributed programming interfaces, such as the Unified Parallel C (UPC) port for the Intel Single-Cloud…”

Section: Related Workmentioning

confidence: 99%

Inter-kernel communication facility of a distributed operating system for NoC-based lightweight manycores

Penna

Souto

Uller

et al. 2021

Journal of Parallel and Distributed Computing

View full text Add to dashboard Cite

Lightweight manycore processors deliver high performance and scalability by bundling in a single chip hundreds of low-power cores, a distributed memory architecture and Networks-on-Chip (NoCs). Operating Systems (OSes) for these processors feature a distributed design, in which a communication layer enables kernels to exchange information and interoperate. Currently, this communication infrastructure is based on mailboxes, which enable fixed-size message exchanges with low latency. However, this solution is suboptimal because it can neither fully exploit the NoC nor efficiently handle the diversity of OS communication protocols. We propose an Inter-Kernel Communication (IKC) facility that exposes two kernel-level communication abstractions in addition to mailboxes: syncs, for enabling a process to signal and unlock another process remotely, and portals, for handling dense data transfers with high bandwidth. We implemented the proposed facility in Nanvix, the only open-source distributed OS that runs on a baremetal lightweight manycore, and we evaluated our solution on a 288-core processor (Kalray MPPA-256). Our results showed that our IKC facility achieves up to 16.87× and 1.68× better performance than a mailbox -only solution, in synchronization and dense data transfers, respectively.

show abstract

“…Overall, they find that GPUs deliver the best performance, the FPGAs demonstrate the best energy efficiency, and the Xeon Phi is easiest to program but shows mediocre results (both run times and energy efficiency). Varghese et al [176] discuss their experiences with the Adapteva Epiphany 64-core network-on-chip co-processor. They consider the device to be suitable for exascale computing due to its energy-efficiency, but programming is difficult due to the low-level primitives and the relatively slow external shared memory interface.…”

Section: :21mentioning

confidence: 99%

The Landscape of Exascale Research

et al. 2020

View full text Add to dashboard Cite

The next generation of supercomputers will break the exascale barrier. Soon we will have systems capable of at least one quintillion (billion billion) floating-point operations per second (10 18 FLOPS). Tremendous amounts of work have been invested into identifying and overcoming the challenges of the exascale era. In this work, we present an overview of these efforts and provide insight into the important trends, developments, and exciting research opportunities in exascale computing. We use a three-stage approach in which we (1) discuss various exascale landmark studies, (2) use data-driven techniques to analyze the large collection of related literature, and (3) discuss eight research areas in depth based on influential articles. Overall, we observe that great advancements have been made in tackling the two primary exascale challenges: energy efficiency and fault tolerance. However, as we look forward, we still foresee two major concerns: the lack of suitable programming tools and the growing gap between processor performance and data bandwidth (i.e., memory, storage, networks). Although we will certainly reach exascale soon, without additional research, these issues could potentially limit the applicability of exascale computing.

show abstract

Programming the Adapteva Epiphany 64-Core Network-on-Chip Coprocessor

Cited by 29 publications

References 12 publications

Efficient parallel execution of genetic algorithms on Epiphany manycore processor

Efficient parallel execution of genetic algorithms on Epiphany manycore processor

Inter-kernel communication facility of a distributed operating system for NoC-based lightweight manycores

The Landscape of Exascale Research

Contact Info

Product

Resources

About