Progress and Challenges in VLSI Placement Research

Markov, Igor L.; Hu, Jin; Kim, Myungchul

doi:10.1109/jproc.2015.2478963

Cited by 74 publications

(24 citation statements)

References 166 publications

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“…Density force modeling remains quite a controversial problem [31] in quadratic placement, where the best location of anchor point for each object is usually unclear. RQL [45] nullifies the top 10% density force vectors to suppress overspreading of standard cells, while the empirical tuning lacks theoretical support and may not guarantee convergence.…”

Section: E Advantage Analysismentioning

confidence: 99%

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ePlace-MS: Electrostatics-Based Placement for Mixed-Size Circuits

Zhuang

Chen

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-We propose eP lace-M S, an electrostatics based placement algorithm for large-scale mixed-size circuits. ePlace-MS is generalized, flat, analytic and nonlinear. The density modeling method eDensity is extended to handle the mixedsize placement. We conduct detailed analysis on the correctness of the gradient formulation and the numerical solution, as well as the rationale of direct-current removal and the advantages over prior density functions. Nesterov's method is used as the nonlinear solver, which shows high yet stable performance over mixed-size circuits. The steplength as the inverse of Lipschitz constant of the gradient function, while we develop a backtracking method to prevent overestimation. An approximated nonlinear preconditioner is developed to minimize the topological and physical differences between large macros and standard cells. Besides, we devise a simulated annealer to legalize the layout of macros and use a second-phase global placement to reoptimize the standard cell layout. All the above innovations are integrated into our mixed-size placement prototype ePlace-MS, which outperforms all the related works in literature with better quality and efficiency. Compared to the leading-edge mixed-size placer NTUplace3 [13], ePlace-MS produces up to 22.98% and on average 8.22% shorter wirelength over all the sixteen modern mixed-size (MMS) benchmark circuits with the same runtime.

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Section: E Advantage Analysismentioning

confidence: 99%

“…LACEMENT remains crucial and challenging in VLSI physical design [22], [31]. Placement performance impacts downstream design phases of clock tree synthesis [27], dynamic power minimization [28], global and detailed routing [30], and etc.…”

mentioning

confidence: 99%

ePlace-MS: Electrostatics-Based Placement for Mixed-Size Circuits

Zhuang

Chen

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Wirelength is one of the most important metrics, since minimizing wirelength is not only a beneficial but also fundamental step to optimize other metrics, such as timing, power, and routability. Therefore, Markov et al [2] pointed out that designing more efficient wirelength-driven placer is the key step to conquer new emerging challenges in placement problem.…”

Section: Introductionmentioning

confidence: 99%

POLAR: A High Performance Mixed-Size Wirelengh-Driven Placer With Density Constraints

Lin

Chu

Shinnerl

et al. 2015

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Wirelength is one of the most important metrics in the placement problem. Minimizing wirelength is not only beneficial, but also a fundamental step to optimize other metrics, such as timing, power, and routability. In this paper, we propose a high performance mixed-size wirelengh-driven placer called POLAR. POLAR is based on the recent popular look-ahead legalization idea. The goals of our look-ahead legalization are: 1) to achieve a roughly legalized placement and 2) to maintain cells' relative positions of quadratic placement while minimizing cell movements. To achieve these goals, in POLAR, look-ahead legalization is realized in a simple and elegant manner. Firstly, all placement density hotspots (where placement overflow occurs) are detected. Secondly, for each hotspot, an appropriate window is searched to cover it by enumerating many feasible candidates. Finally, cell-to-bin assignment is performed within each window by a fast recursive bisection method. The experimental results verify the efficiency of POLAR over the ISPD 2005 and 2006 benchmarks.

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“…Note that a net may contain more than two cells, i.e., a net may be a hyperedge. Given a rectangular ½0; W Â ½0; H; VLSI placement seeks a placement of circuit cells such that no cell overlaps with the other, and the total wirelength is minimized [1,4,14]. This problem is NP-complete [6], and is rather difficult to solve due to the very large scale and NP-completeness.…”

Section: Introductionmentioning

confidence: 99%

“…This problem is NP-complete [6], and is rather difficult to solve due to the very large scale and NP-completeness. However, up to now, there are a number of packages for the VLSI placement problem using different optimization methods [1,4,14].…”

Section: Introductionmentioning

confidence: 99%

Nesterov’s Smoothing and Excessive Gap Methods for an Optimization Problem in VLSI Placement

Chen

Cui

Wang

2014

J. Oper. Res. Soc. China

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In this paper, we propose an algorithm for a nonsmooth convex optimization problem arising in very large-scale integrated circuit placement. The objective function is the sum of a large number of Half-Perimeter Wire Length (HPWL) functions and a strongly convex function. The algorithm is based on Nesterov's smoothing and excessive gap techniques. The main advantage of the algorithm is that it can capture the HPWL information in the process of optimization, and every subproblem has an explicit solution in the process of optimization. The convergence rate of the algorithm is Oð1=k 2 Þ; where k is the iteration counter, which is optimal. We also present preliminary experiments on nine placement contest benchmarks. Numerical examples confirm the theoretical results.

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Progress and Challenges in VLSI Placement Research

Cited by 74 publications

References 166 publications

ePlace-MS: Electrostatics-Based Placement for Mixed-Size Circuits

ePlace-MS: Electrostatics-Based Placement for Mixed-Size Circuits

POLAR: A High Performance Mixed-Size Wirelengh-Driven Placer With Density Constraints

Nesterov’s Smoothing and Excessive Gap Methods for an Optimization Problem in VLSI Placement

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