Progress and challenges of tungsten-filled through-silicon via

Triyoso, Dina H.; Dao, Thuy; Kropewnicki, Tom; Mart́ınez, F.; Noble, R.; Hamilton, Michael C.

doi:10.1109/icicdt.2010.5510274

Cited by 10 publications

(4 citation statements)

References 2 publications

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“…As shown in figure 10, the CNT-Cu composite material and tungsten are occupying unique positions with low resistivities and CTEs. However, tungsten is very costly, and only used as via plugs between on-chip interconnect layers [43]. Overall, the CNT-Cu material represents the best combination of properties with high electronic conductivity and low CTEs for TSV interconnects.…”

Section: Resultsmentioning

confidence: 99%

Vertically aligned CNT-Cu nano-composite material for stacked through-silicon-via interconnects

Sun

Edwards

et al. 2016

Nanotechnology

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For future miniaturization of electronic systems using 3D chip stacking, new fine-pitch materials for through-silicon-via (TSV) applications are likely required. In this paper, we propose a novel carbon nanotube (CNT)/copper nanocomposite material consisting of high aspect ratio, vertically aligned CNT bundles coated with copper. These bundles, consisting of hundreds of tiny CNTs, were uniformly coated by copper through electroplating, and aspect ratios as high as 300:1 were obtained. The resistivity of this nanomaterial was found to be as low as ∼10(-8) Ω m, which is of the same order of magnitude as the resistivity of copper, and its temperature coefficient was found to be only half of that of pure copper. The main advantage of the composite TSV nanomaterial is that its coefficient of thermal expansion (CTE) is similar to that of silicon, a key reliability factor. A finite element model was set up to demonstrate the reliability of this composite material and thermal cycle simulations predicted very promising results. In conclusion, this composite nanomaterial appears to be a very promising material for future 3D TSV applications offering both a low resistivity and a low CTE similar to that of silicon.

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Section: Resultsmentioning

confidence: 99%

Vertically aligned CNT-Cu nano-composite material for stacked through-silicon-via interconnects

Sun

Edwards

et al. 2016

Nanotechnology

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“…In addition, aluminum and other metals are used as conductor-filling materials. To sum up, which material to choose for filling depends on the purpose of the manufactured silicon via [ 35 ]. At present, the copper sulfate process system is mainly used for filling copper in TSV electroplating.…”

Section: Tsv Technology Process and Developmentmentioning

confidence: 99%

Research of Vertical via Based on Silicon, Ceramic and Glass

Tian

2023

Micromachines

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With the increasing demand for high-density integration, low power consumption and high bandwidth, creating more sophisticated interconnection technologies is becoming increasingly crucial. Three-dimensional (3D) integration technology is known as the fourth-generation packaging technology beyond Moore’s Law because of its advantages of low energy consumption, lightweight and high performance. Through-silicon via (TSV) is considered to be at the core of 3D integration because of its excellent electrical performance, lower power consumption, wider bandwidth, higher density, smaller overall size and lighter weight. Therefore, the particular emphasis of this review is the process flow of TSV technology. Among them, the research status of TSV hole etching, deep hole electroplating filling and chemical mechanical planarization (CMP) in TSV preparation process are introduced in detail. There are a multitude of inevitable defects in the process of TSV processing; thus, the stress problems and electrical characteristics that affect the reliability of TSV are summarized in this review. In addition, the process flow and process optimization status of through ceramic via (TCV) and through glass via (TGV) are discussed.

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“…However, when tungsten is used to fill a 3D trench mold with a high aspect ratio and narrow pitch, distortion, such as the bending of the mold, occurs by deposition stress in the metal thin films [8]- [10]. Fig.…”

Section: Introductionmentioning

confidence: 99%

Stress Analysis of Tungsten Deposition in a 3D Trench Mold With Regard to Initial Nuclei Shape

et al. 2022

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Tungsten has been commonly used for fine interconnects due to its good gap-filling characteristics in 3D molds, such as trench patterns. However, tungsten shows high deposition stress. This causes mold distortion because tungsten has low ad-atom mobility, and diffusion-driven relaxation does not occur. To reduce tungsten's deposition stress, the shape of the nuclei can be controlled, which is an effective way to suppress the mechanical deformation caused by the formation of a grain boundary between free surfaces during the coalescence stage. In this study, elliptical tungsten nuclei with various aspect ratios, which suppress coalescence in the early stage of deposition, were proposed to reduce the deposition stress. Stress was calculated using the finite element method (FEM) in the range of 0.5 to 8 radius ratios of the tungsten nuclei. The bending of the trench mold was calculated due to tungsten stress and additional coalescence between films during the filling process. As a result, the wider the elliptical nucleus was, the lower the film stress, and mold bending between line patterns was also reduced. The defects in the depth and width of the periodic trench influenced the mold bending in the early growth stage and the stage of coalescence between films, respectively.

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Progress and challenges of tungsten-filled through-silicon via

Cited by 10 publications

References 2 publications

Vertically aligned CNT-Cu nano-composite material for stacked through-silicon-via interconnects

Vertically aligned CNT-Cu nano-composite material for stacked through-silicon-via interconnects

Research of Vertical via Based on Silicon, Ceramic and Glass

Stress Analysis of Tungsten Deposition in a 3D Trench Mold With Regard to Initial Nuclei Shape

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