Progressive self-learning photomask defect classification

Lynn, Eric C.; Chen, Shih‐Ying; Hsu, T. H.; Hung, Chang-Cheng; Lin, Chin-Hsiang

doi:10.1117/12.477012

Cited by 2 publications

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“…A negative resist is suitable for active and poly layers. 4. Better e-beam data writing priority and speed control Two steps can improve throughput.…”

Section: Simplify the Opc And/or Psm Mask Data Treatmentsmentioning

confidence: 99%

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Mask cost and cycle time reduction

et al. 2003

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In the IC industry the mask cost and cycle time have increased dramatically since the chip design has become more complex and the required mask specification, tighter. The lithography technology has been driven to 65-nm node and 90-nm product will be manufacturing in 2004, according to ITRS's roadmap. However, the optical exposure tools do not extend to a shorter wavelength as the critical dimension (CD) shrinks. In such sub-wavelength technology generation, the mask error factor (MEF) is normally higher. Higher MEF means that tighter mask specification is required to sustain the lithography performance. The tighter mask specification will impact both mask processing complexity and cost. The mask is no longer a low-cost process. In addition, the number of wafers printed from each mask set is trending down, resulting in a huge investment to tape out a new circuit. Higher cost discourages circuit shrinking, thus, prohibits commercialization of new technology nodes.How to reduce the mask cost and cycle time? Robust mask processes will play a crucial role but it is an extreme challenge for the mask-processing people. For example, the blank mask provided by the vender has been coated with the resist. Each batch of blank masks needs to find an optimal dose to meet the rigorous CD specification, since these coating blanks are sent out to the mask house in different periods and through different transportation conditions. The cycle time and the data size also increase drastically when higher transistor density is demanded and smaller pattern jags are created by the aggressive OPC. The vacuum, heating and fogging effects will worsen the process control of the e-beam writer due to a long writing time. The well-controlled transmission and phase shift changes after the cleaning process also become crucial, when an Att-PSM consisting of lines and spaces is fabricated. Dry cleaning may be one possible solution. The mask cost contributed from the defect inspection process has risen significantly, since the price of next generation tool increased but the throughput decreased. After the implementation of model-based OPC, the circuit layout is full of small jig and jag patterns making the failure rate of defect repair higher. In order to reduce cycle time and mask cost, the optimization of both OPC Downloaded From: http://proceedings.spiedigitallibrary.org/ on 06/21/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx algorithm and circuit design needs the closer cooperation between designers, wafer process engineers and mask makers. A close linking of wafer processing, mask making, and OPC as found in captive mask houses is becoming indispensable.

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“…A negative resist is suitable for active and poly layers. 4. Better e-beam data writing priority and speed control Two steps can improve throughput.…”

Section: Simplify the Opc And/or Psm Mask Data Treatmentsmentioning

confidence: 99%

“…(4) Processing: The baker, developer, etcher, stripper and metrology tool are all involved in the mask fabrication. The improvement of each individual tool is essential to achieve the rigorous specification of the next-generation mask.…”

Section: Introductionmentioning

confidence: 99%