Prompt trigger primitives for a self-seeded track trigger

Abstract

A viable self-seeded track trigger for a high rate collider detector environment must have excellent angular precision, response times commensurate with beam crossing rate and low mass. We have designed a fast clustering block servicing 128 contiguous strips to be included in an LHC upgrade silicon strip front end ASIC (ABC130) with these objectives in mind. The block is based on the presence of an analog front end with binary (threshold determined) strip readout latched at each beam crossing. Combinatorial logic tests for the presence of one or two adjacent strips over threshold, a qualifying cluster, at each beam crossing and transmits up to two, eight bits clusters descriptors, specifying address and cluster width via a high speed LVDS output. It is envisioned that a correlator chip, presently in conception, receives this data and via look-up tables checks for coincident hits between silicon strip layers. Since the clustering output will report the presence of one or two hit strips, a half strip pitch (∼40 um for the ATLAS detector) resolution may be possible for each cluster. Our timing results show that the combinatorial clustering logic will settle within 6 ns. Assuming a beam crossing rate of 40 MHz, 16 bits of serialized data can be shifted out at 640MHz each crossing. This will allow a beam synchronous update rate providing data for up to two clusters for each bank of 128 strips. The data latency into the correlator chip will be only two crossings.Present power estimates suggest that the fast cluster block with LVDS driver will consume less than 12 mW.

Development of a Fast Cluster Finding self-seeded trigger demonstrator

“…Detailed description of the FCF and its implementation in the ABC130 chip can be found in ref. [3,4].…”

“…The concept of self-seeded track trigger and the design of the FCF in the context of the ATLAS Phase-II upgrade have been discussed in refs. [2,3]. In this paper, we present the development of a self-seeded trigger demonstrator that uses an FPGA-based correlator to process the FCF data from a sensor doublet.…”

CBC2: a microstrip readout ASIC with coincidence logic for trigger primitives at HL-LHC

“…A hybrid module consisting of one strip and one pixel detector is being considered for the inner tracker, where higher segmentation in η is necessary to maintain acceptable occupancy and resolution [7]. Another approach based on 3D vertical interconnections is described in [8], whilst a stub-finding readout scheme for ATLAS is presented in [9].…”

A self seeded first level track trigger for ATLAS

“…The frontend filtering algorithms used [3], the cluster size [7] and offset method, are shortly summarised here. Their implementation in the frontend ASIC was presented at this workshop [8].…”