“…The input step, however, can be considered as ideal if the logic gate is driven by a logic gate of a similar size. Indeed, as demonstrated in [38,39] and shown in Figure 3, if we assume the input signal as a linear ramp with rise time, T, as long as T ∼ τ o , the error between the actual PD and the value estimated by (3) remains lower than 20%. Conversely, (3) fails to predict the PD if the rise time of the input step is significant (i.e., T τ o ), as in the case of a large logic gate driven by a minimum size one.…”