2008
DOI: 10.1002/cta.524
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Propagation delay of an RC‐circuit with a ramp input: An analytical very accurate and simple model

Abstract: SUMMARYIn this letter, one of the models reported in Mita et al. (IEEE Trans. Circuits Syst.-II: Express Briefs 2007; 54(1):66-70) for estimating the propagation delay of an RC-chain with a linear input is revised and improved. The extended model, while maintaining the same simplicity, has a reduced error which is six times lower than the original model, being always as low as 1%.

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Cited by 5 publications
(6 citation statements)
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“…The input step, however, can be considered as ideal if the logic gate is driven by a logic gate of a similar size. Indeed, as demonstrated in [38,39] and shown in Figure 3, if we assume the input signal as a linear ramp with rise time, T, as long as T ∼ τ o , the error between the actual PD and the value estimated by (3) remains lower than 20%. Conversely, (3) fails to predict the PD if the rise time of the input step is significant (i.e., T τ o ), as in the case of a large logic gate driven by a minimum size one.…”
Section: Evaluating the Parameters Of The Delay Modelmentioning
confidence: 91%
See 1 more Smart Citation
“…The input step, however, can be considered as ideal if the logic gate is driven by a logic gate of a similar size. Indeed, as demonstrated in [38,39] and shown in Figure 3, if we assume the input signal as a linear ramp with rise time, T, as long as T ∼ τ o , the error between the actual PD and the value estimated by (3) remains lower than 20%. Conversely, (3) fails to predict the PD if the rise time of the input step is significant (i.e., T τ o ), as in the case of a large logic gate driven by a minimum size one.…”
Section: Evaluating the Parameters Of The Delay Modelmentioning
confidence: 91%
“…However, this case is generally avoided in practical design; in the vast majority of cases, we can assume the input step as ideal. The rise time and the propagation delay are normalized with respect to the time-constant of the single-pole system [38,39].…”
Section: Evaluating the Parameters Of The Delay Modelmentioning
confidence: 99%
“…where C i is the i-th capacitance in the RC tree and R ik is the total resistance shared by the paths between the source node and nodes i and k [31,89,90,125,142] (the resistances R ik are the sums of stacked transistors resistances, and the capacitances C i are the inter-nodal capacitances). Indeed, stacked transistors can be approximated by a simple RC ladder structure (which is a particular case of an RC tree) and the source voltage is given by V DD or ground nodes.…”
Section: Elmore Delaymentioning
confidence: 99%
“…As we all known, the RC loading of gate lines in LTPS panel can be equivalent to a one-dimensional RC-chain circuit. In 1947, Elmore model [1] was raised to solve the transient response of linear networks of RC circuit, and after that some reports [2][3] presented to modify and optimize Elmore model, and some scientists [4][5] also have proposed new ways to solve this problems. But most of them are not as simple and practical as Elmore Model.…”
Section: Introductionmentioning
confidence: 99%