Properties Incompleteness Evaluation by Functional Verification

Fedeli, A.; Fummi, Franco; Pravadelli, Graziano

doi:10.1109/tc.2007.1012

Cited by 37 publications

(13 citation statements)

References 25 publications

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“…As an opposite class of approaches, coverage metrics have been widely studied for qualification of assertions [13][14][15][16]. Most of these works relies on mutation…”

Section: Related Workmentioning

confidence: 99%

“…Thus, a qualification phase to identify the most interesting assertions is necessary to focus designer's attention on relevant assertions that capture ex-pected (or unexpected) behaviours implemented in the DUV. Unfortunately, as the number of mined assertions can be very high, their manual qualification is almost impractical, while current approaches for automatic evaluation are still unsatisfactory from the point of view either of the effectiveness [9][10][11][12] or of the efficiency [13][14][15][16].…”

Section: Introductionmentioning

confidence: 99%

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Automatic Generation and Qualification of Assertions on Control Signals: A Time Window-Based Approach

Danese¹,

Filini²,

Ghasempouri³

et al. 2016

VLSI-SoC: Design for Reliability, Security, and Low Power

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Assertion-based verification (ABV) is a promising approach for proving that the design implementation is consistent with the designer's intents. However, ABV effectiveness depends on the quality of the assertions that are defined to capture the designer's intents. Assertions are generally defined by verification engineers that manually convert informal specifications in logic formulas according to their expertise. However, manual definition is a time-consuming and error-prone activity, which may fail to exhaustively cover either the intended specification or the implemented behaviours. For this reason, different mining approaches have been recently proposed for the automatic generation of assertions. Unfortunately, in most cases, existing mining tools generate a set of over-constrained assertions. As a consequence, each assertion in the set is a long formula that describes a very specific behaviour of the design under verification (DUV). Thus, in the effort of covering as much DUV behaviours as possible, these approaches generate a huge amount of assertions with a negative impact on the total time required for their verification. To overcome this drawback, this paper introduces a dynamic approach that incrementally analyses control signals on DUV execution traces for mining more expressive temporal assertions that better capture the I/O communication protocol. Then, to evaluate the effectiveness of the generated assertions in covering the intended behaviours, a technique is proposed to estimate assertion's interestingness by ranking them according to metrics typically adopted in the context of data mining.

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“…As an opposite class of approaches, coverage metrics have been widely studied for qualification of assertions [13][14][15][16]. Most of these works relies on mutation…”

Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Automatic Generation and Qualification of Assertions on Control Signals: A Time Window-Based Approach

Danese¹,

Filini²,

Ghasempouri³

et al. 2016

VLSI-SoC: Design for Reliability, Security, and Low Power

Self Cite

View full text Add to dashboard Cite

show abstract

“…In order to detect more latent implementation errors proactively and focus on more necessary functional behaviors for a software system, we perform analogy enumeration based on the original set of key properties, which are constructed in the traditional model checking phase. According to the survey of patterns in property specifications [20][21][22], most properties (more than 90%) could be formulized within five kinds of property patterns, where each of them could be either specified as a Linear Temporal Logic (LTL) formula or a Computation Tree Logic (CTL) formula. As shown in Table 1, we present the original specifications (OS) and its analogy set (AS) for each kind of property patterns, respectively.…”

Section: Constructing the Analogy Set For Key Propertiesmentioning

confidence: 99%

A Latent Implementation Error Detection Method for Software Validation

Zhou

Liu

et al. 2013

Journal of Applied Mathematics

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Model checking and conformance testing play an important role in software system design and implementation. From the view of integrating model checking and conformance testing into a tightly coupled validation approach, this paper presents a novel approach to detect latent errors in software implementation. The latent errors can be classified into two kinds, one is called as Unnecessary Implementation Trace, and the other is called as Neglected Implementation Trace. The method complements the incompleteness of security properties for software model checking. More accurate models are characterized to leverage the effectiveness of the model-based software verification and testing combined method.

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“…Many papers followed this concept, e.g. [7], [8], [9], [10], [11], [12], [13]. But still the main problem of these approaches is the sheer number of possible mutations.…”

Section: Introductionmentioning

confidence: 99%

A guiding coverage metric for formal verification

Haedicke¹,

Grosse²,

Drechsler³

2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Abstract-Considerable effort is made to verify the correct functional behavior of circuits and systems. To guarantee the overall success metric-driven verification flows have been developed. In these flows coverage metrics are omnipresent. Well established coverage metrics for simulation-based verification approaches exist. This is however not the case for formal verification where property checking is a major technique to prove the correctness of the implementation.In this paper we present a guiding coverage metric for this formal verification setting. Our metric reports a single number describing how much of the circuit behavior is uniquely determined by the properties. In addition, the coverage metric guides the verification engineer to achieve completeness by providing helpful information about missing scenarios. This information comes from a new behavior classification algorithm which determines uncovered behavior classes for a signal and allows to compute the coverage of a signal. To measure the complete circuit behavior we devise a coverage metric for a set of signals. The metric is calculated by partitioning the coverage computation into a safe part and an unsafe part where the latter one is weighted accordingly using recursion. This procedure takes into account that in practice properties refer to internal signals which in turn need to be covered them-self. Overall, our metric allows to track the verification progress in property checking and significantly aid the verification engineers in completing the property set.

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Properties Incompleteness Evaluation by Functional Verification

Cited by 37 publications

References 25 publications

Automatic Generation and Qualification of Assertions on Control Signals: A Time Window-Based Approach

Automatic Generation and Qualification of Assertions on Control Signals: A Time Window-Based Approach

A Latent Implementation Error Detection Method for Software Validation

A guiding coverage metric for formal verification

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