Properties of CeOx/La2O3 gate dielectric and its effects on the MOS transistor characteristics

Epitaxial, well-ordered ceria/lanthana high-k gate dielectrics on silicon

“…18 In excellent agreement with our results, those authors speculated that the excess oxygen is transferred from the cerium oxide into the lanthana film and the underlying interface to silicon, thereby effectively annihilating oxygen vacancies. Here, using the complementary combination of XSW-HAXPES and XSW-XRF, we have shown that the additional oxygen introduced into the structure also serves to improve the crystallinity of the lanthana starting about two atomic layers from the interface.…”

“…This postprocessing step at comparatively low temperatures of 500 C, which is compatible with a gate-last process, 18 enables the growth of highly ordered, C-type La 2 O 3 (111) films with a low defect concentration, which was shown to result in reduced Coulomb scattering by reducing the fixed oxide charge, reduced leakage currents, and a higher channel mobility, 18,19 suggesting that also the modest interface postoxidation helps in improving the electrical properties of the gate stack. Together with the prepassivation approach, these findings may pave the road toward the realization of rare-earth based, epitaxial, highly crystalline high-k oxides on silicon.…”

“…14 Very recently, a strong improvement in electrical properties was observed when a thin cerium oxide was deposited on top, which was explained in a scenario where, driven by the difference in oxygen chemical potential in lanthana and ceria, oxygen vacancies at the interface and in the LaO x film were speculated to be healed by additional oxygen ions provided by the ceria adlayer. [17][18][19] Earlier, we have reported the beneficial use of an atomic layer of chlorine for substrate passivation, enabling the growth of well-ordered Ce 2 O 3 (111) (Refs. 20 and 21) and Pr 2 O 3 (111) (Ref.…”

Improving the electrical characteristics of MOS transistors with CeO2/La2O3 stacked gate dielectric

“…Using certain alloy forms or complex oxides where the desirable electrical properties can be tailored is a promising technique [1,[7][8][9]. Meanwhile, a special measure for overcoming the high oxygen vacancies of high-k materials based on the oxygen chemical potential control to the film was proposed recently [10][11][12][13]. It was recently found that multivalent cerium (Ce) can significantly improve the characteristics of MOS devices using La 2 O 3 as gate dielectric film [10,12].…”

(Invited) High-K Evolution: Subnanometer EOT Challenges and Future Perspectives for Scaling

“…5), the multivalent CeO 2 capping layer can supply the additional oxygen that suppresses the oxygen vacancies in bulk La 2 O 3 and promotes the silicon or La-Si oxidation. This reaction would help to improve the quality of the La 2 O 3 /Si interface layer and thus would lead to better electrical characteristics of the devices (25)(26)(27). It may be noted that this multi-layer structure would not be a possible option for fabricating dielectric in the half nanometer EOT range as the overall thickness would be too large.…”