Properties of extremely thin silicon layer in silicon-on-insulator structure formed by smart-cut technology

Popov, V.; Antonova, I. V.; Stas, V.F.; Mironova, L. V.; Гутаковский, А. К.; Спесивцев, Е. В.; Mardegzhov, A.S; Franznusov, A.A; Feofanov, G. N.

doi:10.1016/s0921-5107(99)00437-7

Cited by 36 publications

(14 citation statements)

References 13 publications

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“…Paper origin of these donors is debatable, although the formation of donors is often observed in SOI structure fabricated with different methods [9,10]. Formation of acceptor centers with shallow levels is also observed in the top silicon layer and the substrate of SOI structures implanted with the highest dose either oxygen or nitrogen.…”

Section: Originalmentioning

confidence: 99%

Pressure related defect engineering in silicon‐on‐insulator‐like structures produced by either oxygen or nitrogen ion implantation

Antonova

2006

Physica Status Solidi (b)

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Pressure-related effects in silicon-on-insulator-like structures fabricated in either nitrogen or oxygen implanted silicon during subsequent annealing are analyzed. Among them are the removal of radiation defects from the top silicon layer, some degradation of the buried insulator, pressure dependence of charges at the Si/SiO 2 (or Si/SiN x ) interface, formation of the electrically active centers in the top silicon layer and the substrate.

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Section: Originalmentioning

confidence: 99%

Pressure related defect engineering in silicon‐on‐insulator‐like structures produced by either oxygen or nitrogen ion implantation

Antonova

2006

Physica Status Solidi (b)

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“…Srikrishnan [20] forms (by implantation) an etch stop layer inside of the transferred with Smart-Cut silicon film with a subsequent etching. Popov et al [21] reports a layer-bylayer oxidation (of the film transferred with Smart-Cut) with subsequent stripping in diluted HF for thinning of the layer. All listed approaches increase SOI wafer production cost and degrade thickness uniformity.…”

Section: Introductionmentioning

confidence: 99%

Transfer of Single Crystalline Silicon Nanolayer Onto Alien Substrate

Usenko¹,

Carr

Chen

2004

IEEE Trans. Nanotechnology

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Starting from the 60-nm node, future generations of mainstream semiconductor devices (i.e., CMOS) will be mostly manufactured from silicon-on-insulator (SOI) initial substrates with the top silicon layer having a thickness 50 nm or less. We describe a process that is capable for transfer of nanoscale thick layers. The layer is delaminated from a single crystalline silicon substrate and laminated onto another substrate, thus resulting in SOI. The process includes: 1) forming a trap layer for hydrogen in an initial substrate; 2) delivery of hydrogen to the traps by diffusion of monatomic hydrogen; 3) evolving the trapped hydrogen into a layer of hydrogen platelets; 4) stiffening of the surface of the initial substrate by laminating to another substrate; and 5) delaminating a layer from the initial substrate along the hydrogen platelet layer. Details of the new layer transfer process are described. A depth where the buried trap layer locates is critical for the process. An implantation of heavy ions is used to form the trap layer. A trap capacity for hydrogen is evaluated as a function of implantation conditions. Plasma hydrogenation is used to deliver atomic hydrogen to the traps. Electron cyclotron resonance, microwave, RF, and dc plasma are compared as the hydrogenation sources. Dependence of a thickness of a transferred layer as a function of the mass of implanted ions and implantation energy is described. Types of layer transfer faults are also described. Mechanisms of the layer transfer faults are suggested. We discuss limits of scaling down of the thickness of the layer that is transferred from one substrate to another. The scaling limit of our process is compared to the limits of other (SIMOX, Smart-Cut, and ELTRAN) processes.

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“…The transient layer is practically absent at the bonded interface. 6 As a result, the trap energies lie in the relatively narrow interval of values E c -0.17 to E c -0.37 eV.…”

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confidence: 96%

Traps at the bonded interface in silicon-on-insulator structures

Antonova¹,

Naumova²,

Nikolaev³

et al. 2001

Applied Physics Letters

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In this study, we compared the trap density distributions, D it , in the band gap of silicon at the Si/thermal SiO 2 interface and at the bonded interface of the silicon-on-insulator structure, deduced from deep level transient spectroscopy measurements. The trap energies for the bonded Si/SiO 2 interface are localized in the range from E c -0.17 to E c -0.37 eV. The lack of the transient SiO x layer at the bonded interface is suggested to lead to a relatively narrow interval of trap energies.

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Properties of extremely thin silicon layer in silicon-on-insulator structure formed by smart-cut technology

Cited by 36 publications

References 13 publications

Pressure related defect engineering in silicon‐on‐insulator‐like structures produced by either oxygen or nitrogen ion implantation

Pressure related defect engineering in silicon‐on‐insulator‐like structures produced by either oxygen or nitrogen ion implantation

Transfer of Single Crystalline Silicon Nanolayer Onto Alien Substrate

Traps at the bonded interface in silicon-on-insulator structures

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