Traps at the bonded interface in silicon-on-insulator structures

Antonova, I. V.; Naumova, O. V.; Nikolaev, D. V.; Popov, V.; Stano, J.; Skuratov, V.A.

doi:10.1063/1.1428412

Cited by 12 publications

(4 citation statements)

References 3 publications

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“…7,8 In this method, the energy levels contributing predominantly to the Q-DLTS signal at a current temperature and chosen time window were calculated from the equation…”

Section: Experimental and Resultsmentioning

confidence: 99%

“…Recently, we showed that the spectrum of traps at a bonded Si/SiO 2 interface substantially differs from that at an Si/SiO 2 interface prepared by thermal oxidation. 7,8 This difference was attributed to the absence of the transition SiO x layer at the bonded interface or/and intense neutralization of traps by hydrogen due to utilization of hydrogen slicing technology ͑hydrogen implantation in one of the bonded wafers͒. The concentration of hydrogen present in SOI during fabrication can be lowered if one uses BESOI technology.…”

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confidence: 96%

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Comparison of Electrical Properties of Silicon-on-Insulator Structures Fabricated with Use of Hydrogen Slicing and BESOI

Antonova

Nikolaev

Naumova

et al. 2004

Electrochem. Solid-State Lett.

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The top silicon layers and the bonded Si/SiO 2 interfaces in silicon-on-insulator ͑SOI͒ structures fabricated by ͑i͒ wafer bonding and hydrogen slicing, and (ii) by wafer bonding and chemical mechanical thinning ͑back-etch SOI, BESOI͒ were investigated and compared by charge deep-level transient spectroscopy. The hydrogen slicing was provided by hydrogen implantation into one of the bonded wafers and led to the high hydrogen concentration during SOI fabrication. Hydrogen presented in SOI during the fabrication process partially neutralizes the traps at the Si/thermal SiO 2 interface, and completely neutralizes shallow acceptors and contamination with deep levels in the top silicon layer.The conventional Si/SiO 2 interface prepared by thermal oxidation of silicon has a transition SiO x layer 2 nm thick. 1 It is, namely, the transition SiO x layer that determines the spectrum of interface traps. 2 Recently, a new method to create the Si/SiO 2 interface was developed. It is bonding of a silicon wafer with an oxidized one. 3 Bonding technology is now a promising way to create new structures for microelectronics. 3,4 Particularly, different silicon -on-insulator ͑SOI͒ structures are fabricated with use of bonding technology ͓for example, Smart-Cut technology 5 and back-etch SOI ͑BESOI 6 ͔͒. Recently, we showed that the spectrum of traps at a bonded Si/SiO 2 interface substantially differs from that at an Si/SiO 2 interface prepared by thermal oxidation. 7,8 This difference was attributed to the absence of the transition SiO x layer at the bonded interface or/and intense neutralization of traps by hydrogen due to utilization of hydrogen slicing technology ͑hydrogen implantation in one of the bonded wafers͒. The concentration of hydrogen present in SOI during fabrication can be lowered if one uses BESOI technology. 6 In this case we did not use hydrogen implantation, and a thinning of the top silicon layer was performed with polishing and etching.The aim of this study was to compare interface traps and centers with deep and shallow levels in the top silicon layers of two different SOI types: ͑i͒ structures prepared by hydrogen slicing, 7,8 and (ii) BESOI structure. 6 The final heat-treatment of both SOI was annealing at high temperature ͑ϳ1100°C͒. The result was that hydrogen concentration was decreased dramatically and became lower than the sensitivity of secondary-ion mass spectroscopy ͑SIMS͒. 9 Introduction of shallow acceptors, centers with deep levels, and higher density of the interface traps was observed in BESOI structures. A high concentration of hydrogen in the first type of SOI leads to neutralization of all contamination and a decrease in interface density. Experimental and ResultsTo fabricate the SOI structures, Czochralski ͑Si-CZ͒ and float zone ͑Si-FZ͒ grown silicon wafers with n-type conductivity were used. SOI structures fabricated by hydrogen slicing were marked as SOI-A. The BESOI structures were marked as SOI-B. The type of initial silicon ͑FZ or CZ͒ was added to the SOI designation. Both SOI-A and S...

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“…7,8 In this method, the energy levels contributing predominantly to the Q-DLTS signal at a current temperature and chosen time window were calculated from the equation…”

Section: Experimental and Resultsmentioning

confidence: 99%

mentioning

confidence: 96%

Comparison of Electrical Properties of Silicon-on-Insulator Structures Fabricated with Use of Hydrogen Slicing and BESOI

Antonova

Nikolaev

Naumova

et al. 2004

Electrochem. Solid-State Lett.

Self Cite

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“…It should be mentioned that in simulations, the traps energy level, density, and distribution in the interface (D it ) are defined according to [22][23][24][25].…”

Section: Pixel Descriptionmentioning

confidence: 99%

3D device‐level simulation of charge separation from sidewall in vertical transfer gate pinned photodiode pixels for noise mitigation

Heidari

Alaibakhsh

Karami

2020

IET Circuits, Devices & Systems

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This study proposes vertical sidewall implantation for noise reduction of CMOS image sensor pixel employing a vertical transfer gate (VTG). The pixel performance is evaluated by 3D device-level simulation. It is concluded that the proposed pixel's output is less sensitive to interface traps compared to similar previous work. In previous backside illuminated shared VTG pixel, which lacks the sidewall implantation for noise mitigation, photogenerated carriers were transferred to the floating diffusion (FD) region along with the interface. In the proposed pixel, the channel is separated from the interface, and photogenerated carriers are transferred with 10 nm distance from VTG. The proposed pixel has a complete charge transfer from the buried pinned photodiode to FD with 1274 e − /µm 2 equilibrium full-well capacity. The conversion gain is 200 μV/e − and the signal-to-noise ratio is 37 dB.

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“…When the annealing temperature increases from 900 to 1100°C, the trap density decreases from 2 · 10 12 cm À2 to 2.5 · 10 11 cm À2 . An information about the activation energy of the traps located at the Si/SiO 2 interface for bulk materials was obtained by deep level transient spectroscopy [9]. The values are located in the 0.17-0.37 eV interval.…”

Section: Introductionmentioning

confidence: 99%