2011
DOI: 10.1016/j.egypro.2011.06.117
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Properties of high efficiency silicon heterojunction cells

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Cited by 32 publications
(18 citation statements)
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“…The operating temperature of PV modules can be quite high, and the temperature coefficient, i.e., the efficiency loss per unit change in temperature, is an important parameter. With values of about 0:45%=K for diffused-junction solar cells, high-quality SHJ devices outperform their conventional counterparts in the field with values < 0:25%=K [116,172]. The smaller temperature sensitivity is mainly due to the high V oc of SHJ devices [27].…”
Section: Operation In the Fieldmentioning
confidence: 99%
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“…The operating temperature of PV modules can be quite high, and the temperature coefficient, i.e., the efficiency loss per unit change in temperature, is an important parameter. With values of about 0:45%=K for diffused-junction solar cells, high-quality SHJ devices outperform their conventional counterparts in the field with values < 0:25%=K [116,172]. The smaller temperature sensitivity is mainly due to the high V oc of SHJ devices [27].…”
Section: Operation In the Fieldmentioning
confidence: 99%
“…Consequently there is a strong drive for SHJ devices to move to alternative metallization schemes. Recently, good results were achieved using either additional busbars (total of 5) on 6 6 inch 2 pseudo square wafers [116], or densely spaced metallic wires, replacing the busbars using technology developed by Day4 Energy in Canada [117]. An encapsulated SHJ cell with a certified efficiency of 19.3% was achieved using the latter scheme [117].…”
Section: Metallizationmentioning
confidence: 99%
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“…Recently, a record cell efficiency of 23.7% (on 100Â100 mm 2 ) has been presented 1 and several groups have achieved efficiencies of well above 20%. 2,3 Unlike many other high efficiency concepts, the silicon heterojunction concept is based on a rather simple processing scheme consisting of plasma enhanced chemical vapour deposition (PECVD), sputtering and screen printing steps, and all processing steps are carried out at temperatures below 200 to 250 C. The high efficiencies likely originate from low minority carrier recombination rates at the c-Si wafer surfaces passivated by thin layers of intrinsic amorphous silicon (a-Si:H). Without passivation, silicon surface states related to unsaturated and reconstructed dangling bonds are likely causing a rather high surface recombination rate.…”
Section: Introductionmentioning
confidence: 99%
“…The world record 23.7% SRJ devices of Sanyo was indeed achieved with a wafer only 98 micron thick [2]. The high Vo c translates into favorable temperature coefficient for the module perfonnance, and values well below -O.3%;oC are reported [3]. …”
Section: Basic Principlesmentioning
confidence: 99%