Proposal and Investigation of Area Scaled Nanosheet Tunnel FET: A Physical Insight

Srivastava, Shobhit; Panwar, Sourabh; Acharya, Abhishek

doi:10.1109/ted.2022.3184915

Cited by 19 publications

(2 citation statements)

References 27 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The influence of source/drain extension length on electrical parameters with and without considering self-heating effect is highlighted in nanosheet FET. The digital as well as analog performance for this NRFET is studied including self-heating effect [26]. Likewise, the effect of self-heating in three channel T shape nanosheet FET is highlighted by Shobhit et al [27].…”

Section: Introductionmentioning

confidence: 92%

Study on trap sensitivity for single material gate and double material gate nano-ribbon FETs

Rai,

Sharma,

Saha

et al. 2024

Phys. Scr.

View full text Add to dashboard Cite

In this work, the trap sensitivity of single material gate (SMG) and dual material gate (DMG) nano ribbon FETs (NRFETs) are reported using TCAD Sentaurus Device simulator. The trap sensitivity is extracted for Gaussian trap distribution of both acceptor and donor type traps. We have reported the trap sensitivity for the variation in trap concentration, energy peak position, work function of metal gate, and temperature for both the NRFETs. It is realized that trap sensitivity is greater and lesser than 100% for acceptor type trap in SMG and DMG NRFETs, respectively, whereas, such sensitivity is 147% and 123% for donor type trap concentration, respectively. Temperature also shows a significant variation in trap sensitivity for both the NRFETs. The increase in work function leads to the reduction in trap sensitivity for both NRFETs in existence of acceptor and donor trap charges. The maximum sensitivity in trap are 400% and 275% for SMG and DMG NRFETs, respectively, in presence of donor trap concentration. Moreover, the trap sensitivity is very insignificant at high gate bias for donor type trap concentration with wide variation in parameters.

show abstract

Section: Introductionmentioning

confidence: 92%

Study on trap sensitivity for single material gate and double material gate nano-ribbon FETs

Rai,

Sharma,

Saha

et al. 2024

Phys. Scr.

View full text Add to dashboard Cite

show abstract

“…Instead of using Si material throughout all four areas in the FBFET device, the Ch-2 and drain regions are built of Si 1−x Ge x material, whereas the source and Ch-1 regions are composed of Si material to improve the overall performance of the device. The technical literature [27][28][29] has already reported the fabrication of lateral Si-SiGe heterostructures. There have also been reports in the literature [30,31] regarding the creation of devices having three sharp N+ to P+ junctions.…”

Section: Device Structure and Operational Principlementioning

confidence: 99%

Design and performance analysis of Si-SiGe heterostructure based double gate feedback FET

Das,

Katta,

Raj

et al. 2024

Phys. Scr.

View full text Add to dashboard Cite

The design and performance analysis of a Si-SiGe heterostructure-based double gate feedback field-effect transistor (HDG FBFET) are presented in this paper. The proposed HDG FBFET is capable of providing high on current (3×10−4 A/μm) with a large ION /IOFF ratio (3×1011) and is scalable up to 20 nm channel length. Its exceptionally steep switching characteristics (SS〈 1 mV/decade) and ability to switch ON/OFF at lower gate voltage due to the use of smaller band-gap material (Si1−xGex) in channel-2 and drain regions make it suitable for use in low power applications. A significant hysteresis window of 4.99 V is also achieved by the device, which can be extremely helpful for memory applications. Moreover, a comprehensive investigation of the nature of hysteresis in relation to the different device parameters has also been carried out. The designing of the device structure and all of the electrical performance characterization have been done using the Sentaurus TCAD tool.

show abstract

Epitaxial Layer‐Based Si/SiGe Hetero‐Junction Line Tunnel FETs

Acharya,

Panwar,

Srivastava

et al. 2023

Advanced Ultra Low‐Power Semiconductor Devices

View full text Add to dashboard Cite

Proposal and Investigation of Area Scaled Nanosheet Tunnel FET: A Physical Insight

Cited by 19 publications

References 27 publications

Study on trap sensitivity for single material gate and double material gate nano-ribbon FETs

Study on trap sensitivity for single material gate and double material gate nano-ribbon FETs

Design and performance analysis of Si-SiGe heterostructure based double gate feedback FET

Epitaxial Layer‐Based Si/SiGe Hetero‐Junction Line Tunnel FETs

Contact Info

Product

Resources

About