Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis

Hara, Yutaka; Tomiyama, Hiroyuki; Honda, Shinya; Takada, Hiroaki

doi:10.2197/ipsjjip.17.242

Cited by 241 publications

(115 citation statements)

References 4 publications

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“…The second section presents an evaluation of the work done in this thesis with a single case study: A TTA processor is created and the compression ratio and resulting power savings are estimated in a CHStone test suite [5] using two different NOP removal template configurations. Then the power consumption of the ring buffer and shift register fetch designs for variable length instructions are estimated through synthesis and simulation on a 40 nm ASIC technology node.…”

Section: Verification and Evaluationmentioning

confidence: 99%

“…CHStone [5] is a C-based high-level synthesis benchmark suite with programs from various application domains. Each of them contains C-code which is translated into a program image using tcecc and PIG, and outputs a T or F value at the end of the test.…”

Section: Chstone Benchmark Suitementioning

confidence: 99%

“…The efficiency of the code compression is gauged by creating a custom TTA processor with a maximum instruction length of 256 bits and minimum length of 32 bits for the CHStone [5] test suite. Each test program's code for the processor is compressed using four and eight instruction templates.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Variable length instruction compression on Transport Triggered Architectures

Helkala

Viitanen

Kultala

et al. 2014

2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV)

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The Static Random-Access Memory (SRAM) modules used for embedded microprocessor devices consume a large portion of the whole system's power. The memory module consumes static power on keeping awake and dynamic power on memory accesses. The power dissipation of the instruction memory can be limited by using code compression methods, which reduce the memory size. The compression may require the use of variable length instruction formats in the processor. The powerefficient design of variable length instruction fetch and decode units is challenging for static multiple-issue processors, because such architectures have simple hardware to begin with, as they aim for very low power consumption on embedded platforms. The power saved by using these compression approaches, which necessitate more complex logic, is easily lost on inefficient processor design.This thesis proposes an implementation for instruction template-based compression, its decompression and two instruction fetch design alternatives for variable length instruction encoding on Transport Triggered Architecture (TTA), a static multiple-issue exposed data path architecture. Both of the new fetch and decode units are integrated into the TTA-based Co-design Environment (TCE), which is a toolset for rapid designing and prototyping of processors based on TTA.The hardware description of the fetch units is verified on a register transfer level and benchmarked using the CHStone test suite. Furthermore, the fetch units are synthesized on a 40 nm standard cell Application Specific Integrated Circuit (ASIC) technology library for area, performance and power consumption measurements. The power cost of the variable length instruction support is compared to the power savings from memory reduction, which is evaluated using HP Labs' CACTI tool.The compression approach reaches an average program size reduction of 44% at best with a set of test programs, and the total power consumption of the system is reduced. The thesis shows that the proposed variable length fetch designs are sufficiently low-power oriented for TTA processors to benefit from the code compression.

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Section: Verification and Evaluationmentioning

confidence: 99%

Section: Chstone Benchmark Suitementioning

confidence: 99%

See 1 more Smart Citation

Variable length instruction compression on Transport Triggered Architectures

Helkala

Viitanen

Kultala

et al. 2014

2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV)

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“…We applied the pattern discovery approach described above to identify commonly occurring patterns in a suite of 13 C benchmark programs -the 12 CHStone HLS benchmarks [10], as well as dhrystone. Table 2 presents a sharing analysis for 6 patterns we found to be common.…”

Section: Pattern Sharing Analysismentioning

confidence: 99%

Impact of FPGA architecture on resource sharing in high-level synthesis

Hadjis

Canis

Anderson

et al. 2012

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays

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Resource sharing is a key area-reduction approach in highlevel synthesis (HLS) in which a single hardware functional unit is used to implement multiple operations in the highlevel circuit specification. We show that the utility of sharing depends on the underlying FPGA logic element architecture and that different sharing trade-offs exist when 4-LUTs vs. 6-LUTs are used. We further show that certain multi-operator patterns occur multiple times in programs, creating additional opportunities for sharing larger composite functional units comprised of patterns of interconnected operators. A sharing cost/benefit analysis is used to inform decisions made in the binding phase of an HLS tool, whose RTL output is targeted to Altera commercial FPGA families: Stratix IV (dual-output 6-LUTs) and Cyclone II (4-LUTs).

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“…First, we verify its accuracy by comparing the cycle profiling results produced by LEAP with those produced by our For all results in this section, we target the Altera Cyclone II FPGA and profile programs on the DE2 board (which contains 8 MB of SDRAM). A set of 13 C-language benchmarks are used: the twelve CHStone [14] benchmarks plus Dhrystone [29], a traditional integer benchmark. CHStone represents a wide array of applications, including encoding and decoding, double-precision mathematics, encryption, and image decompression.…”

Section: Experimental Studymentioning

confidence: 99%

Low-cost hardware profiling of run-time and energy in FPGA embedded processors

Anderson

Brown

Canis

2011

ASAP 2011 - 22nd IEEE International Conference on Application-Specific Systems, Architectures and Processors

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Abstract-This paper introduces a low-overhead hardware profiling architecture, called LEAP, that attains real-time cycle and energy profiles of an FPGA-based soft processor. A novel technique is used to associate profiling data with specific functions in a way that is area-and power-efficient. Results show that relative to a previously-published hardware profiler, our design uses up to 18× less area and 8.6× less energy. LEAP is designed to be extensible for a variety of profiling tasks, three of which are investigated in this paper. We also demonstrate the utility of LEAP in the context of hardware/software co-design of processor/accelerator FPGA-based systems.

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Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis

Cited by 241 publications

References 4 publications

Variable length instruction compression on Transport Triggered Architectures

Variable length instruction compression on Transport Triggered Architectures

Impact of FPGA architecture on resource sharing in high-level synthesis

Low-cost hardware profiling of run-time and energy in FPGA embedded processors

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