Prospect of tunneling green transistor for 0.1V CMOS

Abstract

Well designed tunneling green transistor may enable future VLSIs operating at 0.1V. Sub-60mV/decade characteristics have been convincingly demonstrated on 8" wafers. Large I ON at low V DD are possible according to TCAD simulations but awaits verification. V DD scaling will greatly benefit from low (effective) band gap energy, which may be provided by type II heterojunctions of Si/Ge or compound semiconductors.A Looming Barrier to IC Scaling Reducing the voltage V DD is a powerful way to reduce IC energy consumption, which is proportional to V DD 2 . Power usage was kept under control when V DD was reduced in proportion to half-pitch up to 130nm as shown in Fig 1 [1]. The 14nm node is projected to operate at 0.7V, making the power consumption 25x larger than it would be if operated at 0.14V as the past trend suggests. While IC power consumption has been much discussed as a thermal management challenge, it is also responsible for a few percent of the electricity usage and growing fast. MOSFET current cannot rise faster than one decade for every 60mV increase in V g (the subthreshold swing, SS). To reduce V DD to 0.14V with I ON /I OFF ratio of mere 3 decades, SS needs to be 45mV/decade. A low voltage transistor (Green Transistor, gFET) is needed.Green Transistor with Steep Turn On/Off In MOSFETs (and BJTs), a potential barrier is raised and lowered by V g to turn the current on and off (Fig. 2). Due to Boltzmann distribution, some electrons always have sufficient energy to pass over the barrier. The current can only be reduced by the rate of electron density drop with increasing energy, hence the 60 mV/decade limit [1]. To beat this limit, the carriers must not flow over a barrier. They may tunnel through it. Fig. 3 shows a prototype tunnel transistor [1][2][3][4]. Electrons are generated by band-to-band tunneling in the P+ source when the gate voltage bends the energy band to satisfy two conditions-overlap of the valence and conduction bands and the a high electric field or thin tunnel barrier [5]. The generated electrons flow through the surface N-channel to the drain. Fig. 4 shows simulated I d -V g [6] assuming uniform source doping. In all > 3E19 cm -3 cases, steep turn on occurs at the onset of band overlap. Unfortunately the graded source doping profile and the averaging effect of the Poisson equation provide a continuous range of (effective) doping concentration near the tip of the source. At points of lower doping (Fig. 4) the turn-on voltages and electric field (therefore I ON ) are both lower. The envelope of these curves is the IV of a prototype tunnel transistor, with a disappointing sub-V t swing.

Modeling and simulation of low power ferroelectric non-volatile memory tunnel field effect transistors using silicon-doped hafnium oxide as gate dielectric

“…The tunneling field effect transistors have been investigated intensely in recent years [8] due to their considerable potentials for ultra-low power applications [9,10]. Using the advantages of both ferroelectric thin films for data storage and TFETs as energy efficient devices, it is possible to design a new class of nonvolatile memories, with a relatively large memory window, fast writing, nondestructive read-out operation, and low power consumption.…”

Subthreshold-swing physics of tunnel field-effect transistors

“…However, TFETs suffer from low ON-current mainly because of the large band-to-band tunneling (BTBT) barrier, especially for large band gap semiconductors including silicon, the material of choice for mainstream semiconductor technology. To overcome this shortcoming and further improve the subthreshold characteristics, many efforts [1][2][3][4][5][6][7][8][9][10][11] have been focused on proposing new structures/materials for TFETs, among which several [2][3][4] exhibit near perfect (step-like) switching characteristics, i.e., ultra-small SS. However, the hidden physics and design rules leading to such ideal subthreshold characteristics are still not apparent.…”

Novel Si–Ge–C superlattices and their applications

“…Tunnel heterojunction MOSFETs promise ultra-low voltage operation [3], but suffer from low ON-state current due to the low efficiency of band-to-band tunneling in indirect band-gaps of source-to-channel heterojunctions [4]. Devices made on ultra-thin SOI substrates, have an ON-state current much closer to that of Thermionic-MOSFETs, although the physics behind this enhancement has not been discussed in detail [31].…”

“…Another major barrier to the desirable trends captured by Moore's Law, is the problem of power dissipation, which has led to the growing interest in Tunnel-MOSFETs, which offer a solution to this problem [3]. While the type of band offsets needed for Tunnel-NMOS can be obtained with SiGe random alloys strained to Si, the same is not true for the band offsets needed for Tunnel-PMOS.…”