Prospective and Critical Issues of III-V/Ge CMOS on Si Platform

Abstract

III-V/Ge CMOS on Si platform, realized by heterogeneous integration, is expected to provide a variety of applications from high speed logic CMOS to versatile SoC chips, where various functional devices can be co-integrated. Among them, high speed/low power logic CMOS using III-V/Ge channels are promising device solution for further progress in scaled CMOS. While many critical issues have been well recognized for them, we present possible solutions to break through these difficulties in this paper. Main critical issues of Ge/III-V MOSFETs on Si platform are (1) formation of MIS gate stacks with superior interfacial properties and (2) formation of Ge/III-V channel layers on Si substrates. Ge MOS interfaces with thermally-oxidized GeO 2 are promising for the superior interface properties as well as the high inversion-layer mobility. SGOI/GOI structures based on Ge condensation are promising for future ultrathin SGOI/GOI MOSFETs. A wafer bonding technique can be potential solutions of III-V MOSFETs on Si platform. Using this technique, the operation of ultrathin body/ultrathin BOX InGaAs-OI MOSFETs are demonstrated. Also, surface nitridation and surface orientation engineering are shown to be effective in III-V MOS interface control. Finally, novel metal S/D InGaAs MOSFETs utilizing NiInGaAs alloys are proposed and demonstrated.

Atomic layer deposited tantalum silicate on crystallographically-oriented epitaxial germanium: interface chemistry and band alignment

“…1 In so doing, device designers have sought to mitigate direct-tunneling gate leakage current, which is exponential in nature, while maintaining superior gate-channel electrostatic coupling. 31 Moreover, the process compatibility of future low-power technologies [7][8][9][10][11][12][13][16][17][18]32,33 with existing Si CMOS infrastructure remains a key industry objective.…”

“…These coupled effects must be investigated in order to fully-utilize Ge-based technologies going forward. 2,3 Whereas much recent work 4–30 has focused on the HfO 2 /Al 2 O 3 composite/bi-layer high- κ dielectric combined with an interfacial passivation layer (IPL), typically based on GeO 2 , it remains difficult to achieve sub-nm EOT. Thus, new passivation schemes have been proposed to realize highly uniform, compositionally abrupt, temperature-stable, and highly-scaled high- κ dielectric/Ge MOS interfaces.…”

“…In order to address the above challenges, extensive dielectric research has been performed over the last two decades, with little success in finding simple (non-composite, or non-binary) dielectric systems that mimic the electrical and thermodynamic stability of the SiO 2 /Si interface. 4–38 One promising dielectric, tantalum oxide (Ta 2 O 5 ), and its silicate (TaSiO x or (Ta 2 O 5 ) 1− x (SiO 2 ) x ), has recently found renewed interest as a potential high- κ dielectric for the Ge 39–49 and III–V 50–53 material systems. TaSiO x was shown to achieve excellent device performance when integrated within a composite TaSiO x /InP gate stack (on In x Ga 1− x As-channel FETs), exhibiting low interfacial defect density ( D it ), low gate leakage current density ( J g ), and high drive current ( I ON ).…”

Low Temperature Effect on Strained and Relaxed Ge pFinFETs STI Last Processes

“…The lower effective mass of germanium compared to silicon makes it a reasonably attractive material for future high-performance applications, since high hole mobility material is required for p-type channel devices (1). In combination with the FinFET architecture, which presents a strong electrostatic coupling (2), it gives rise to a promising future device, namely, a Ge pFinFET.…”

Limiting Factors of Channel Mobility in III-V/Ge MOSFETs

“…Particularly, understanding of limiting factors of the III-V/Ge MOS channel mobility is of paramount importance, because the high current drive is the purpose of introducing these materials. Among a variety of technological issues for realizing Ge/III-V MOSFETs [5,6], the gate stack technologies and MOS channel engineering can substantially affect the MOS channel mobility and the current drive. In this paper, thus, we address key issues for enhancing channel mobility in InGaAs/Ge MOSFETs with an emphasis on the gate stack and channel formation technologies of InGaAs/Ge MOSFETs.…”