ProTaR: An Infrastructure IP for Repairing RAMs in System-on-Chips

A Survey of Yield Modeling and Yield Enhancement Methods

“…Also included in such circuits is built-in self-test circuitry, built-in redundancy analysis, and self-repair/reconfiguration circuitry to enable automated test and reconfiguration [22]- [28]. Many algorithms have been developed to enable automatic reconfiguration, including circuitry that optimizes shared test and reconfiguration resources for system-on-chips with hundreds of heterogeneous memory blocks [29]- [32]. ECCs store data with additional bits so that if there are single bit errors, these are detected and corrected.…”

“…Next, response surfaces are fit to the data to determine linear, quadratic [14], [56], [103], [104], [108], [109] or more complex nonlinear functions [110], that model the relationship between the parameters and circuit performances. These models are then used to determine the indicator function, using (29), where z(p, q) = 1 for parameters that result in performances that satisfy all specifications.…”

Efficient Memory Repair Using Cache-Based Redundancy

“…A controller coordinates the spare resources allocation by receiving signals from the built-in self-test (BIST) circuitry regarding the localization of the faulty part. Examples of such techniques can be seen in [17]- [33]. A fully associative cache is employed in [17], [18] to replace faulty words.…”

A bit level area aware cache-based architecture for memory repairs

“…A controller receives information regarding the localisation of the faulty part from a BIST circuitry and coordinates the allocation process. Examples of such techniques can be seen in [6]- [15]. In [6], a column-based approach is investigated, using hardwired remapping of the spares.…”

“…In [14], additional rows and IOs are proposed in a BISR solution for multi-port RAMs. A complete platform for test and repair of multiple memories is given in [15], using spare rows and columns for repairs. BISR architectures are characterised by a tradeoff between the best utilisation of the spare resources against the remapping process and the associated routing circuitry.…”